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Searched refs:REG_READ (Results 1 – 25 of 604) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
80 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
282 regs->cdv.saveADPA = REG_READ(ADPA); in cdv_save_display_registers()
332 temp = REG_READ(DPLL_A); in cdv_restore_display_registers()
335 REG_READ(DPLL_A); in cdv_restore_display_registers()
338 temp = REG_READ(DPLL_B); in cdv_restore_display_registers()
[all …]
H A Dgma_display.c117 REG_READ(map->base); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
218 REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
287 REG_READ(map->base); in gma_crtc_dpms()
294 REG_READ(map->conf); in gma_crtc_dpms()
638 REG_READ(map->fp0); in gma_crtc_restore()
641 REG_READ(map->fp1); in gma_crtc_restore()
[all …]
H A Dcdv_intel_display.c151 *val = REG_READ(SB_DATA); in cdv_sb_read()
202 REG_READ(DPIO_CFG); in cdv_sb_reset()
475 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
483 REG_READ(OV_OVADD); in cdv_disable_sr()
499 fw = REG_READ(DSPFW1); in cdv_update_wm()
506 fw = REG_READ(DSPFW2); in cdv_update_wm()
535 REG_READ(FW_BLC_SELF); in cdv_update_wm()
717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
749 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
80 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
282 regs->cdv.saveADPA = REG_READ(ADPA); in cdv_save_display_registers()
332 temp = REG_READ(DPLL_A); in cdv_restore_display_registers()
335 REG_READ(DPLL_A); in cdv_restore_display_registers()
338 temp = REG_READ(DPLL_B); in cdv_restore_display_registers()
[all …]
H A Dgma_display.c117 REG_READ(map->base); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
218 REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
287 REG_READ(map->base); in gma_crtc_dpms()
294 REG_READ(map->conf); in gma_crtc_dpms()
638 REG_READ(map->fp0); in gma_crtc_restore()
641 REG_READ(map->fp1); in gma_crtc_restore()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/gma500/
H A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
80 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
282 regs->cdv.saveADPA = REG_READ(ADPA); in cdv_save_display_registers()
332 temp = REG_READ(DPLL_A); in cdv_restore_display_registers()
335 REG_READ(DPLL_A); in cdv_restore_display_registers()
338 temp = REG_READ(DPLL_B); in cdv_restore_display_registers()
[all …]
H A Dgma_display.c117 REG_READ(map->base); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
218 REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
287 REG_READ(map->base); in gma_crtc_dpms()
294 REG_READ(map->conf); in gma_crtc_dpms()
638 REG_READ(map->fp0); in gma_crtc_restore()
641 REG_READ(map->fp1); in gma_crtc_restore()
[all …]
H A Dcdv_intel_display.c151 *val = REG_READ(SB_DATA); in cdv_sb_read()
202 REG_READ(DPIO_CFG); in cdv_sb_reset()
475 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
483 REG_READ(OV_OVADD); in cdv_disable_sr()
499 fw = REG_READ(DSPFW1); in cdv_update_wm()
506 fw = REG_READ(DSPFW2); in cdv_update_wm()
535 REG_READ(FW_BLC_SELF); in cdv_update_wm()
717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
749 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9002_calib.c457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); in hubbub2_wm_read_state()
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); in hubbub2_wm_read_state()
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); in hubbub2_wm_read_state()
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); in hubbub2_wm_read_state()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); in hubbub2_wm_read_state()
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); in hubbub2_wm_read_state()
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); in hubbub2_wm_read_state()
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); in hubbub2_wm_read_state()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); in hubbub2_wm_read_state()
521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); in hubbub2_wm_read_state()
522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); in hubbub2_wm_read_state()
528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); in hubbub2_wm_read_state()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
567 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
595 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
599 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
632 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
567 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
595 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
599 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
632 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
567 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
595 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
599 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
632 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
[all …]

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