/dports/devel/vc-intrinsics/vc-intrinsics-753ad50/GenXIntrinsics/include/llvm/GenXIntrinsics/ |
H A D | GenXIntrinsics.h | 307 inline GenXIntrinsic::ID getGenXMulIID(bool LHSign, bool RHSign) { in getGenXMulIID() argument 309 ? (RHSign ? GenXIntrinsic::genx_ssmul : GenXIntrinsic::genx_sumul) in getGenXMulIID() 310 : (RHSign ? GenXIntrinsic::genx_usmul : GenXIntrinsic::genx_uumul); in getGenXMulIID()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 653 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 655 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 658 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 661 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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H A D | AMDGPUISelLowering.cpp | 1931 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 1932 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 1936 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 1939 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 654 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 656 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 659 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 662 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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H A D | AMDGPUISelLowering.cpp | 1911 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 1912 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 1916 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 1919 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 784 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 786 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 789 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 792 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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H A D | AMDGPUISelLowering.cpp | 1997 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 1998 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 2002 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 2005 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 784 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 786 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 789 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 792 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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H A D | AMDGPUISelLowering.cpp | 1997 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 1998 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 2002 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 2005 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 784 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 786 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 789 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 792 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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H A D | AMDGPUISelLowering.cpp | 1997 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 1998 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 2002 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 2005 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 775 Value *RHSign = Builder.CreateAShr(Den, K31); in expandDivRem32() local 777 Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign; in expandDivRem32() 780 Den = Builder.CreateAdd(Den, RHSign); in expandDivRem32() 783 Den = Builder.CreateXor(Den, RHSign); in expandDivRem32()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2783 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSDIV_SREM() local 2786 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 2789 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 2799 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSDIV_SREM()
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H A D | AMDGPUISelLowering.cpp | 2052 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 2053 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 2057 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 2060 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2783 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSDIV_SREM() local 2786 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 2789 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 2799 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSDIV_SREM()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3021 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSDIV_SREM() local 3024 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3027 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3037 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSDIV_SREM()
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H A D | AMDGPUISelLowering.cpp | 2066 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM() local 2067 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM() 2071 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM() 2074 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3130 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3133 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3130 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3133 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3016 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSDIV_SREM() local 3019 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3022 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3032 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSDIV_SREM()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3130 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3133 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3199 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3202 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3205 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3236 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3130 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3133 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3016 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSDIV_SREM() local 3019 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3022 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSDIV_SREM() 3032 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSDIV_SREM()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 3130 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset); in legalizeSignedDIV_REM() local 3133 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3136 RHS = B.buildXor(Ty, RHS, RHSign).getReg(0); in legalizeSignedDIV_REM() 3167 auto Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); in legalizeSignedDIV_REM()
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