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Searched refs:RLW (Results 1 – 25 of 88) sorted by relevance

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/dports/emulators/dosbox-staging/dosbox-staging-0.78.0/src/cpu/core_dynrec/
H A Drisc_ppc.h135 #define RLW(op, regs, rega, sh, mb, me, rc) (((op)<<26)|((regs) <<21)|((rega)<<16)| ((sh)<<11)|((m… macro
139 #define RLW_OP(op, regs, rega, sh, mb, me, rc) cache_addd(RLW(op, regs, rega, sh, mb, me, rc))
774 *op++ = RLW(20, FC_OP1, FC_OP1, 24, 0, 7, 0); // rlwimi FC_OP1, FC_OP1, 24, 0, 7 in gen_fill_function_ptr()
777 *op++ = RLW(20, FC_OP1, FC_OP1, 16, 0, 15, 0); // rlwimi FC_OP1, FC_OP1, 16, 0, 15 in gen_fill_function_ptr()
779 *op++ = RLW(23, FC_OP1, FC_RETOP, FC_OP2, 0, 31, 0); // rotlw FC_RETOP, FC_OP1, FC_OP2 in gen_fill_function_ptr()
783 *op++ = RLW(20, FC_OP1, FC_OP1, 8, 16, 23, 0); // rlwimi FC_OP1, FC_OP1, 8, 16, 23 in gen_fill_function_ptr()
786 *op++ = RLW(20, FC_OP1, FC_OP1, 16, 0, 15, 0); // rlwimi FC_OP1, FC_OP1, 16, 0, 15 in gen_fill_function_ptr()
789 *op++ = RLW(23, FC_OP1, FC_RETOP, FC_OP2, 0, 31, 0); // rotlw FC_RETOP, FC_OP1, FC_OP2 in gen_fill_function_ptr()
793 *op++ = RLW(20, FC_OP2, FC_RETOP, 16, 0, 15, 0); // rlwimi FC_RETOP, FC_OP2, 16, 0, 5 in gen_fill_function_ptr()
794 *op++ = RLW(23, FC_RETOP, FC_RETOP, FC_OP3, 0, 31, 0); // rotlw FC_RETOP, FC_RETOP, FC_OP3 in gen_fill_function_ptr()
[all …]
H A Drisc_ppc64le.h132 #define RLW(op, regs, rega, sh, mb, me, rc) (Bit32u)(((op)<<26)|((regs) <<21)|((rega)<<16)| ((sh… macro
138 #define RLW_OP(op, regs, rega, sh, mb, me, rc) cache_addd(RLW(op, regs, rega, sh, mb, me, rc))
867 *op++ = RLW(20, FC_OP1, FC_OP1, 24, 0, 7, 0); // rlwimi FC_OP1, FC_OP1, 24, 0, 7 in gen_fill_function_ptr()
870 *op++ = RLW(20, FC_OP1, FC_OP1, 16, 0, 15, 0); // rlwimi FC_OP1, FC_OP1, 16, 0, 15 in gen_fill_function_ptr()
872 *op++ = RLW(23, FC_OP1, FC_RETOP, FC_OP2, 0, 31, 0); // rotlw FC_RETOP, FC_OP1, FC_OP2 in gen_fill_function_ptr()
876 *op++ = RLW(20, FC_OP1, FC_OP1, 8, 16, 23, 0); // rlwimi FC_OP1, FC_OP1, 8, 16, 23 in gen_fill_function_ptr()
879 *op++ = RLW(20, FC_OP1, FC_OP1, 16, 0, 15, 0); // rlwimi FC_OP1, FC_OP1, 16, 0, 15 in gen_fill_function_ptr()
882 *op++ = RLW(23, FC_OP1, FC_RETOP, FC_OP2, 0, 31, 0); // rotlw FC_RETOP, FC_OP1, FC_OP2 in gen_fill_function_ptr()
886 *op++ = RLW(20, FC_OP2, FC_RETOP, 16, 0, 15, 0); // rlwimi FC_RETOP, FC_OP2, 16, 0, 5 in gen_fill_function_ptr()
887 *op++ = RLW(23, FC_RETOP, FC_RETOP, FC_OP3, 0, 31, 0); // rotlw FC_RETOP, FC_RETOP, FC_OP3 in gen_fill_function_ptr()
[all …]
/dports/science/openbabel/openbabel-3.1.1/test/pdb_ligands_sdf/
H A D4rlw_bun.sdf3 Coordinates from PDB:4RLW:A:201 Model:1 without hydrogens
94 4RLW
/dports/science/aircraft-datcom/aircraft-datcom-ed877bb/src/
H A Dsupdrg.f123 RLW=CT+SIGMA*CRSTAR
124 P=SRSTAR/(RLW*2.*SPANS)
126 ARG1=BETA*SPANS/RLW
H A Dsupltg.f1067 RLW=CT+SIGMA*CRSTAR
1068 P=SRSTAR/(RLW*2.*SPANS)
1070 ARG1=BETA*SPANS/RLW
/dports/devel/avr-gdb/gdb-7.3.1/sim/cr16/
H A Dsimops.c3279 tmp = RLW (addr); in OP_87_8()
3296 tmp = RLW (addr); in OP_12B_14()
3319 tmp = RLW (addr); in OP_46_7()
3336 tmp = RLW (addr); in OP_A_4()
3359 tmp = RLW (addr); in OP_AE_8()
3382 tmp = RLW (addr); in OP_21A_A()
3399 tmp = RLW (addr); in OP_188_14()
3416 tmp = RLW (addr); in OP_128_14()
3431 tmp = RLW (addr); in OP_AF_8()
3447 tmp = RLW (addr); in OP_129_14()
[all …]
H A Dcr16_sim.h447 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/gdb761/gdb-7.6.1/sim/cr16/
H A Dsimops.c3279 tmp = RLW (addr); in OP_87_8()
3296 tmp = RLW (addr); in OP_12B_14()
3319 tmp = RLW (addr); in OP_46_7()
3336 tmp = RLW (addr); in OP_A_4()
3359 tmp = RLW (addr); in OP_AE_8()
3382 tmp = RLW (addr); in OP_21A_A()
3399 tmp = RLW (addr); in OP_188_14()
3416 tmp = RLW (addr); in OP_128_14()
3431 tmp = RLW (addr); in OP_AF_8()
3447 tmp = RLW (addr); in OP_129_14()
[all …]
H A Dcr16_sim.h447 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/v850/
H A Dsim-main.h188 #define RLW(x) load_mem (x, 4) macro
/dports/devel/avr-gdb/gdb-7.3.1/sim/v850/
H A Dsim-main.h188 #define RLW(x) load_mem (x, 4) macro
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/v850/
H A Dsim-main.h188 #define RLW(x) load_mem (x, 4)
/dports/devel/avr-gdb/gdb-7.3.1/sim/d10v/
H A Dsimops.c1427 tmp = RLW (addr); in OP_31000000()
1446 tmp = RLW (addr); in OP_6601()
1467 tmp = RLW (addr); in OP_6201()
1488 tmp = RLW (addr); in OP_6200()
1507 tmp = RLW (addr); in OP_33010000()
H A Dd10v_sim.h468 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/gdb761/gdb-7.6.1/sim/d10v/
H A Dsimops.c1427 tmp = RLW (addr); in OP_31000000()
1446 tmp = RLW (addr); in OP_6601()
1467 tmp = RLW (addr); in OP_6201()
1488 tmp = RLW (addr); in OP_6200()
1507 tmp = RLW (addr); in OP_33010000()
H A Dd10v_sim.h468 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/
H A Dsimops.c1427 tmp = RLW (addr); in OP_31000000()
1446 tmp = RLW (addr); in OP_6601()
1467 tmp = RLW (addr); in OP_6201()
1488 tmp = RLW (addr); in OP_6200()
1507 tmp = RLW (addr); in OP_33010000()
H A Dd10v_sim.h468 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/
H A Dsimops.c1427 tmp = RLW (addr); in OP_31000000()
1446 tmp = RLW (addr); in OP_6601()
1467 tmp = RLW (addr); in OP_6201()
1488 tmp = RLW (addr); in OP_6200()
1507 tmp = RLW (addr); in OP_33010000()
H A Dd10v_sim.h468 #define RLW(x) get_longword(dmem_addr(x)) macro
/dports/devel/gdb761/gdb-7.6.1/sim/v850/
H A Dsim-main.h409 #define RLW(x) load_mem (x, 4) macro
/dports/emulators/mess/mame-mame0226/src/devices/cpu/z8000/
H A Dz8000.h241 inline uint16_t RLW(uint16_t dest, uint8_t twice);
/dports/emulators/mame/mame-mame0226/src/devices/cpu/z8000/
H A Dz8000.h241 inline uint16_t RLW(uint16_t dest, uint8_t twice);
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td186 (instregex "RLW(INM|NM)(8)?$"),
1092 (instregex "RLW(IMI|INM|NM)(8)?_rec$"),
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td186 (instregex "RLW(INM|NM)(8)?$"),
1092 (instregex "RLW(IMI|INM|NM)(8)?_rec$"),

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