1 /* $OpenBSD: rtl81x9reg.h,v 1.36 2006/12/12 10:24:38 reyk Exp $ */ 2 3 #ifndef RTL81X9REG_H 4 #define RTL81X9REG_H 5 6 /* 7 * Copyright (c) 1997, 1998 8 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Bill Paul. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 38 */ 39 40 /* 41 * RealTek 8129/8139 register offsets 42 */ 43 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 44 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 45 #define RL_IDR2 0x0002 46 #define RL_IDR3 0x0003 47 #define RL_IDR4 0x0004 48 #define RL_IDR5 0x0005 49 /* 0006-0007 reserved */ 50 #define RL_MAR0 0x0008 /* Multicast hash table */ 51 #define RL_MAR1 0x0009 52 #define RL_MAR2 0x000A 53 #define RL_MAR3 0x000B 54 #define RL_MAR4 0x000C 55 #define RL_MAR5 0x000D 56 #define RL_MAR6 0x000E 57 #define RL_MAR7 0x000F 58 59 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 60 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 61 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 62 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 63 64 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 65 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 66 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 67 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 68 69 #define RL_RXADDR 0x0030 /* RX ring start address */ 70 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 71 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 72 #define RL_COMMAND 0x0037 /* command register */ 73 #define RL_CURRXADDR 0x0038 /* current address of packet read */ 74 #define RL_CURRXBUF 0x003A /* current RX buffer address */ 75 #define RL_IMR 0x003C /* interrupt mask register */ 76 #define RL_ISR 0x003E /* interrupt status register */ 77 #define RL_TXCFG 0x0040 /* transmit config */ 78 #define RL_RXCFG 0x0044 /* receive config */ 79 #define RL_TIMERCNT 0x0048 /* timer count register */ 80 #define RL_MISSEDPKT 0x004C /* missed packet counter */ 81 #define RL_EECMD 0x0050 /* EEPROM command register */ 82 #define RL_CFG0 0x0051 /* config register #0 */ 83 #define RL_CFG1 0x0052 /* config register #1 */ 84 /* 0053-0057 reserved */ 85 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 86 /* 0059-005A reserved */ 87 #define RL_MII 0x005A /* 8129 chip only */ 88 #define RL_HALTCLK 0x005B 89 #define RL_MULTIINTR 0x005C /* multiple interrupt */ 90 #define RL_PCIREV 0x005E /* PCI revision value */ 91 /* 005F reserved */ 92 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 93 94 /* Direct PHY access registers only available on 8139 */ 95 #define RL_BMCR 0x0062 /* PHY basic mode control */ 96 #define RL_BMSR 0x0064 /* PHY basic mode status */ 97 #define RL_ANAR 0x0066 /* PHY autoneg advert */ 98 #define RL_LPAR 0x0068 /* PHY link partner ability */ 99 #define RL_ANER 0x006A /* PHY autoneg expansion */ 100 101 #define RL_DISCCNT 0x006C /* disconnect counter */ 102 #define RL_FALSECAR 0x006E /* false carrier counter */ 103 #define RL_NWAYTST 0x0070 /* NWAY test register */ 104 #define RL_RX_ER 0x0072 /* RX_ER counter */ 105 #define RL_CSCFG 0x0074 /* CS configuration register */ 106 107 /* 108 * When operating in special C+ mode, some of the registers in an 109 * 8139C+ chip have different definitions. These are also used for 110 * the 8169 gigE chip. 111 */ 112 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 113 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 114 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 115 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 116 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 117 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 118 #define RL_CFG2 0x0053 119 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 120 #define RL_TXSTART 0x00D9 /* 8 bits */ 121 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 122 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 123 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 124 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 125 126 /* 127 * Registers specific to the 8169 gigE chip 128 */ 129 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130 #define RL_PHYAR 0x0060 131 #define RL_TBICSR 0x0064 132 #define RL_TBI_ANAR 0x0068 133 #define RL_TBI_LPAR 0x006A 134 #define RL_GMEDIASTAT 0x006C /* 8 bits */ 135 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 136 #define RL_GTXSTART 0x0038 /* 16 bits */ 137 /* 138 * TX config register bits 139 */ 140 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 141 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 142 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 143 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 145 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146 #define RL_TXCFG_HWREV 0x7C800000 147 148 #define RL_LOOPTEST_OFF 0x00000000 149 #define RL_LOOPTEST_ON 0x00020000 150 #define RL_LOOPTEST_ON_CPLUS 0x00060000 151 152 /* Known revision codes. */ 153 154 #define RL_HWREV_8169 0x00000000 155 #define RL_HWREV_8110S 0x00800000 156 #define RL_HWREV_8169S 0x04000000 157 #define RL_HWREV_8169_8110SB 0x10000000 158 #define RL_HWREV_8169_8110SC 0x18000000 159 #define RL_HWREV_8168_SPIN1 0x30000000 160 #define RL_HWREV_8100E_SPIN1 0x30800000 161 #define RL_HWREV_8101E 0x34000000 162 #define RL_HWREV_8168_SPIN2 0x38000000 163 #define RL_HWREV_8100E_SPIN2 0x38800000 164 #define RL_HWREV_8139 0x60000000 165 #define RL_HWREV_8139A 0x70000000 166 #define RL_HWREV_8139AG 0x70800000 167 #define RL_HWREV_8139B 0x78000000 168 #define RL_HWREV_8130 0x7C000000 169 #define RL_HWREV_8139C 0x74000000 170 #define RL_HWREV_8139D 0x74400000 171 #define RL_HWREV_8139CPLUS 0x74800000 172 #define RL_HWREV_8101 0x74c00000 173 #define RL_HWREV_8100 0x78800000 174 175 #define RL_TXDMA_16BYTES 0x00000000 176 #define RL_TXDMA_32BYTES 0x00000100 177 #define RL_TXDMA_64BYTES 0x00000200 178 #define RL_TXDMA_128BYTES 0x00000300 179 #define RL_TXDMA_256BYTES 0x00000400 180 #define RL_TXDMA_512BYTES 0x00000500 181 #define RL_TXDMA_1024BYTES 0x00000600 182 #define RL_TXDMA_2048BYTES 0x00000700 183 184 /* 185 * Transmit descriptor status register bits. 186 */ 187 #define RL_TXSTAT_LENMASK 0x00001FFF 188 #define RL_TXSTAT_OWN 0x00002000 189 #define RL_TXSTAT_TX_UNDERRUN 0x00004000 190 #define RL_TXSTAT_TX_OK 0x00008000 191 #define RL_TXSTAT_EARLY_THRESH 0x003F0000 192 #define RL_TXSTAT_COLLCNT 0x0F000000 193 #define RL_TXSTAT_CARR_HBEAT 0x10000000 194 #define RL_TXSTAT_OUTOFWIN 0x20000000 195 #define RL_TXSTAT_TXABRT 0x40000000 196 #define RL_TXSTAT_CARRLOSS 0x80000000 197 198 /* 199 * Interrupt status register bits. 200 */ 201 #define RL_ISR_RX_OK 0x0001 202 #define RL_ISR_RX_ERR 0x0002 203 #define RL_ISR_TX_OK 0x0004 204 #define RL_ISR_TX_ERR 0x0008 205 #define RL_ISR_RX_OVERRUN 0x0010 206 #define RL_ISR_PKT_UNDERRUN 0x0020 207 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 208 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 209 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 210 #define RL_ISR_SWI 0x0100 /* C+ only */ 211 #define RL_ISR_CABLE_LEN_CHGD 0x2000 212 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 213 #define RL_ISR_TIMEOUT_EXPIRED 0x4000 214 #define RL_ISR_SYSTEM_ERR 0x8000 215 216 #define RL_INTRS \ 217 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 220 221 #define RL_INTRS_CPLUS \ 222 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 223 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 224 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 225 226 227 /* 228 * Media status register. (8139 only) 229 */ 230 #define RL_MEDIASTAT_RXPAUSE 0x01 231 #define RL_MEDIASTAT_TXPAUSE 0x02 232 #define RL_MEDIASTAT_LINK 0x04 233 #define RL_MEDIASTAT_SPEED10 0x08 234 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 235 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 236 237 /* 238 * Receive config register. 239 */ 240 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 241 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 242 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 243 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 244 #define RL_RXCFG_RX_RUNT 0x00000010 245 #define RL_RXCFG_RX_ERRPKT 0x00000020 246 #define RL_RXCFG_WRAP 0x00000080 247 #define RL_RXCFG_MAXDMA 0x00000700 248 #define RL_RXCFG_BURSZ 0x00001800 249 #define RL_RXCFG_FIFOTHRESH 0x0000E000 250 #define RL_RXCFG_EARLYTHRESH 0x07000000 251 252 #define RL_RXDMA_16BYTES 0x00000000 253 #define RL_RXDMA_32BYTES 0x00000100 254 #define RL_RXDMA_64BYTES 0x00000200 255 #define RL_RXDMA_128BYTES 0x00000300 256 #define RL_RXDMA_256BYTES 0x00000400 257 #define RL_RXDMA_512BYTES 0x00000500 258 #define RL_RXDMA_1024BYTES 0x00000600 259 #define RL_RXDMA_UNLIMITED 0x00000700 260 261 #define RL_RXBUF_8 0x00000000 262 #define RL_RXBUF_16 0x00000800 263 #define RL_RXBUF_32 0x00001000 264 #define RL_RXBUF_64 0x00001800 265 266 #define RL_RXFIFO_16BYTES 0x00000000 267 #define RL_RXFIFO_32BYTES 0x00002000 268 #define RL_RXFIFO_64BYTES 0x00004000 269 #define RL_RXFIFO_128BYTES 0x00006000 270 #define RL_RXFIFO_256BYTES 0x00008000 271 #define RL_RXFIFO_512BYTES 0x0000A000 272 #define RL_RXFIFO_1024BYTES 0x0000C000 273 #define RL_RXFIFO_NOTHRESH 0x0000E000 274 275 /* 276 * Bits in RX status header (included with RX'ed packet 277 * in ring buffer). 278 */ 279 #define RL_RXSTAT_RXOK 0x00000001 280 #define RL_RXSTAT_ALIGNERR 0x00000002 281 #define RL_RXSTAT_CRCERR 0x00000004 282 #define RL_RXSTAT_GIANT 0x00000008 283 #define RL_RXSTAT_RUNT 0x00000010 284 #define RL_RXSTAT_BADSYM 0x00000020 285 #define RL_RXSTAT_BROAD 0x00002000 286 #define RL_RXSTAT_INDIV 0x00004000 287 #define RL_RXSTAT_MULTI 0x00008000 288 #define RL_RXSTAT_LENMASK 0xFFFF0000 289 290 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 291 /* 292 * Command register. 293 */ 294 #define RL_CMD_EMPTY_RXBUF 0x0001 295 #define RL_CMD_TX_ENB 0x0004 296 #define RL_CMD_RX_ENB 0x0008 297 #define RL_CMD_RESET 0x0010 298 299 /* 300 * EEPROM control register 301 */ 302 #define RL_EE_DATAOUT 0x01 /* Data out */ 303 #define RL_EE_DATAIN 0x02 /* Data in */ 304 #define RL_EE_CLK 0x04 /* clock */ 305 #define RL_EE_SEL 0x08 /* chip select */ 306 #define RL_EE_MODE (0x40|0x80) 307 308 #define RL_EEMODE_OFF 0x00 309 #define RL_EEMODE_AUTOLOAD 0x40 310 #define RL_EEMODE_PROGRAM 0x80 311 #define RL_EEMODE_WRITECFG (0x80|0x40) 312 313 /* 9346/9356 EEPROM commands */ 314 315 #define RL_9346_WRITE 0x5 316 #define RL_9346_READ 0x6 317 #define RL_9346_ERASE 0x7 318 #define RL_9346_EWEN 0x4 319 #define RL_9346_EWEN_ADDR 0x30 320 #define RL_9456_EWDS 0x4 321 #define RL_9346_EWDS_ADDR 0x00 322 323 #define RL_EECMD_WRITE 0x5 /* 0101b */ 324 #define RL_EECMD_READ 0x6 /* 0110b */ 325 #define RL_EECMD_ERASE 0x7 /* 0111b */ 326 #define RL_EECMD_LEN 4 327 328 #define RL_EEADDR_LEN0 6 /* 9346 */ 329 #define RL_EEADDR_LEN1 8 /* 9356 */ 330 331 #define RL_EECMD_READ_6BIT 0x180 /* XXX */ 332 #define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ 333 334 #define RL_EE_ID 0x00 335 #define RL_EE_PCI_VID 0x01 336 #define RL_EE_PCI_DID 0x02 337 /* Location of station address inside EEPROM */ 338 #define RL_EE_EADDR 0x07 339 340 /* 341 * MII register (8129 only) 342 */ 343 #define RL_MII_CLK 0x01 344 #define RL_MII_DATAIN 0x02 345 #define RL_MII_DATAOUT 0x04 346 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 347 348 /* 349 * Config 0 register 350 */ 351 #define RL_CFG0_ROM0 0x01 352 #define RL_CFG0_ROM1 0x02 353 #define RL_CFG0_ROM2 0x04 354 #define RL_CFG0_PL0 0x08 355 #define RL_CFG0_PL1 0x10 356 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 357 #define RL_CFG0_PCS 0x40 358 #define RL_CFG0_SCR 0x80 359 360 /* 361 * Config 1 register 362 */ 363 #define RL_CFG1_PWRDWN 0x01 364 #define RL_CFG1_SLEEP 0x02 365 #define RL_CFG1_IOMAP 0x04 366 #define RL_CFG1_MEMMAP 0x08 367 #define RL_CFG1_RSVD 0x10 368 #define RL_CFG1_DRVLOAD 0x20 369 #define RL_CFG1_LED0 0x40 370 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 371 #define RL_CFG1_LED1 0x80 372 373 /* 374 * 8139C+ register definitions 375 */ 376 377 /* RL_DUMPSTATS_LO register */ 378 379 #define RL_DUMPSTATS_START 0x00000008 380 381 /* Transmit start register */ 382 383 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 384 #define RL_TXSTART_START 0x40 /* start normal queue transmit */ 385 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 386 387 /* 388 * Config 2 register, 8139C+/8169/8169S/8110S only 389 */ 390 #define RL_CFG2_BUSFREQ 0x07 391 #define RL_CFG2_BUSWIDTH 0x08 392 #define RL_CFG2_AUXPWRSTS 0x10 393 394 #define RL_BUSFREQ_33MHZ 0x00 395 #define RL_BUSFREQ_66MHZ 0x01 396 397 #define RL_BUSWIDTH_32BITS 0x00 398 #define RL_BUSWIDTH_64BITS 0x08 399 400 /* C+ mode command register */ 401 402 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 403 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 404 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 405 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 406 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 407 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 408 409 /* C+ early transmit threshold */ 410 411 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 412 413 /* 414 * Gigabit PHY access register (8169 only) 415 */ 416 417 #define RL_PHYAR_PHYDATA 0x0000FFFF 418 #define RL_PHYAR_PHYREG 0x001F0000 419 #define RL_PHYAR_BUSY 0x80000000 420 421 /* 422 * Gigabit media status (8169 only) 423 */ 424 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 425 #define RL_GMEDIASTAT_LINK 0x02 /* link up */ 426 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 427 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 428 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 429 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 430 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 431 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 432 433 /* 434 * The RealTek doesn't use a fragment-based descriptor mechanism. 435 * Instead, there are only four register sets, each or which represents 436 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 437 * packet buffer (32-bit aligned!) and we place the buffer addresses in 438 * the registers so the chip knows where they are. 439 * 440 * We can sort of kludge together the same kind of buffer management 441 * used in previous drivers, but we have to do buffer copies almost all 442 * the time, so it doesn't really buy us much. 443 * 444 * For reception, there's just one large buffer where the chip stores 445 * all received packets. 446 */ 447 448 #define RL_RX_BUF_SZ RL_RXBUF_64 449 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 450 #define RL_TX_LIST_CNT 4 451 #define RL_MIN_FRAMELEN 60 452 #define RL_TXTHRESH(x) ((x) << 11) 453 #define RL_TX_THRESH_INIT 96 454 #define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 455 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 456 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES 457 458 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 459 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 460 461 #if 0 462 struct rl_chain_data { 463 u_int16_t cur_rx; 464 caddr_t rl_rx_buf; 465 caddr_t rl_rx_buf_ptr; 466 bus_addr_t rl_rx_buf_pa; 467 468 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 469 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 470 u_int8_t last_tx; 471 u_int8_t cur_tx; 472 }; 473 #endif 474 475 476 /* 477 * The 8139C+ and 8160 gigE chips support descriptor-based TX 478 * and RX. In fact, they even support TCP large send. Descriptors 479 * must be allocated in contiguous blocks that are aligned on a 480 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 481 */ 482 483 /* 484 * RX/TX descriptor definition. When large send mode is enabled, the 485 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 486 * the checksum offload bits are disabled. The structure layout is 487 * the same for RX and TX descriptors 488 */ 489 490 struct rl_desc { 491 volatile u_int32_t rl_cmdstat; 492 volatile u_int32_t rl_vlanctl; 493 volatile u_int32_t rl_bufaddr_lo; 494 volatile u_int32_t rl_bufaddr_hi; 495 }; 496 497 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 498 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 499 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 500 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 501 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 502 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 503 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 504 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 505 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 506 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 507 508 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 509 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 510 511 /* 512 * Error bits are valid only on the last descriptor of a frame 513 * (i.e. RL_TDESC_CMD_EOF == 1) 514 */ 515 516 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 517 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 518 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 519 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 520 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 521 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 522 #define RL_TDESC_STAT_OWN 0x80000000 523 524 /* 525 * RX descriptor cmd/vlan definitions 526 */ 527 528 #define RL_RDESC_CMD_EOR 0x40000000 529 #define RL_RDESC_CMD_OWN 0x80000000 530 #define RL_RDESC_CMD_BUFLEN 0x00001FFF 531 532 #define RL_RDESC_STAT_OWN 0x80000000 533 #define RL_RDESC_STAT_EOR 0x40000000 534 #define RL_RDESC_STAT_SOF 0x20000000 535 #define RL_RDESC_STAT_EOF 0x10000000 536 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 537 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 538 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 539 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 540 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 541 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 542 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 543 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 544 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 545 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 546 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 547 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 548 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 549 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 550 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 551 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 552 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 553 RL_RDESC_STAT_CRCERR) 554 555 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 556 (rl_vlandata valid)*/ 557 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 558 559 #define RL_PROTOID_NONIP 0x00000000 560 #define RL_PROTOID_TCPIP 0x00010000 561 #define RL_PROTOID_UDPIP 0x00020000 562 #define RL_PROTOID_IP 0x00030000 563 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 564 RL_PROTOID_TCPIP) 565 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 566 RL_PROTOID_UDPIP) 567 568 /* 569 * Statistics counter structure (8139C+ and 8169 only) 570 */ 571 struct rl_stats { 572 u_int32_t rl_tx_pkts_lo; 573 u_int32_t rl_tx_pkts_hi; 574 u_int32_t rl_tx_errs_lo; 575 u_int32_t rl_tx_errs_hi; 576 u_int32_t rl_tx_errs; 577 u_int16_t rl_missed_pkts; 578 u_int16_t rl_rx_framealign_errs; 579 u_int32_t rl_tx_onecoll; 580 u_int32_t rl_tx_multicolls; 581 u_int32_t rl_rx_ucasts_hi; 582 u_int32_t rl_rx_ucasts_lo; 583 u_int32_t rl_rx_bcasts_lo; 584 u_int32_t rl_rx_bcasts_hi; 585 u_int32_t rl_rx_mcasts; 586 u_int16_t rl_tx_aborts; 587 u_int16_t rl_rx_underruns; 588 }; 589 590 #define RL_RX_DESC_CNT 64 591 #define RL_TX_DESC_CNT_8139 64 592 #define RL_TX_DESC_CNT_8169 1024 593 594 #define RL_TX_QLEN 64 595 596 #define RL_NTXDESC_RSVD 4 597 598 #define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 599 #define RL_RING_ALIGN 256 600 #define RL_PKTSZ(x) ((x)/* >> 3*/) 601 #ifdef __STRICT_ALIGNMENT 602 #define RE_ETHER_ALIGN 2 603 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 604 #else 605 #define RE_ETHER_ALIGN 0 606 #define RE_RX_DESC_BUFLEN MCLBYTES 607 #endif 608 609 #define RL_TX_DESC_CNT(sc) \ 610 ((sc)->rl_ldata.rl_tx_desc_cnt) 611 #define RL_TX_LIST_SZ(sc) \ 612 (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc)) 613 #define RL_NEXT_TX_DESC(sc, x) \ 614 (((x) + 1) % RL_TX_DESC_CNT(sc)) 615 #define RL_NEXT_RX_DESC(sc, x) \ 616 (((x) + 1) % RL_RX_DESC_CNT) 617 #define RL_NEXT_TXQ(sc, x) \ 618 (((x) + 1) % RL_TX_QLEN) 619 620 #define RL_TXDESCSYNC(sc, idx, ops) \ 621 bus_dmamap_sync((sc)->sc_dmat, \ 622 (sc)->rl_ldata.rl_tx_list_map, \ 623 sizeof(struct rl_desc) * (idx), \ 624 sizeof(struct rl_desc), \ 625 (ops)) 626 #define RL_RXDESCSYNC(sc, idx, ops) \ 627 bus_dmamap_sync((sc)->sc_dmat, \ 628 (sc)->rl_ldata.rl_rx_list_map, \ 629 sizeof(struct rl_desc) * (idx), \ 630 sizeof(struct rl_desc), \ 631 (ops)) 632 633 #define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 634 #define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 635 636 /* see comment in dev/ic/re.c */ 637 #define RL_JUMBO_FRAMELEN 7440 638 #define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 639 640 #define MAX_NUM_MULTICAST_ADDRESSES 128 641 642 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 643 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 644 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 645 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 646 #define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 647 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 648 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 649 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 650 #define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 651 652 struct rl_type { 653 u_int16_t rl_vid; 654 u_int16_t rl_did; 655 }; 656 657 struct rl_mii_frame { 658 u_int8_t mii_stdelim; 659 u_int8_t mii_opcode; 660 u_int8_t mii_phyaddr; 661 u_int8_t mii_regaddr; 662 u_int8_t mii_turnaround; 663 u_int16_t mii_data; 664 }; 665 666 /* 667 * MII constants 668 */ 669 #define RL_MII_STARTDELIM 0x01 670 #define RL_MII_READOP 0x02 671 #define RL_MII_WRITEOP 0x01 672 #define RL_MII_TURNAROUND 0x02 673 674 #define RL_UNKNOWN 0 675 #define RL_8129 1 676 #define RL_8139 2 677 #define RL_8139CPLUS 3 678 #define RL_8169 4 679 680 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 681 (x)->rl_type == RL_8169) 682 683 #if 0 684 struct rl_rxsoft { 685 struct mbuf *rxs_mbuf; 686 bus_dmamap_t rxs_dmamap; 687 }; 688 689 struct rl_txq { 690 struct mbuf *txq_mbuf; 691 bus_dmamap_t txq_dmamap; 692 int txq_descidx; 693 int txq_nsegs; 694 }; 695 696 struct rl_list_data { 697 struct rl_txq rl_txq[RL_TX_QLEN]; 698 int rl_txq_considx; 699 int rl_txq_prodidx; 700 701 bus_dmamap_t rl_tx_list_map; 702 struct rl_desc *rl_tx_list; 703 int rl_tx_free; /* # of free descriptors */ 704 int rl_tx_nextfree; /* next descriptor to use */ 705 int rl_tx_desc_cnt; /* # of descriptors */ 706 bus_dma_segment_t rl_tx_listseg; 707 int rl_tx_listnseg; 708 709 struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT]; 710 bus_dmamap_t rl_rx_list_map; 711 struct rl_desc *rl_rx_list; 712 int rl_rx_prodidx; 713 bus_dma_segment_t rl_rx_listseg; 714 int rl_rx_listnseg; 715 }; 716 717 struct rl_softc { 718 struct device sc_dev; /* us, as a device */ 719 void * sc_ih; /* interrupt vectoring */ 720 bus_space_handle_t rl_bhandle; /* bus space handle */ 721 bus_space_tag_t rl_btag; /* bus space tag */ 722 bus_dma_tag_t sc_dmat; 723 bus_dma_segment_t sc_rx_seg; 724 bus_dmamap_t sc_rx_dmamap; 725 struct arpcom sc_arpcom; /* interface info */ 726 struct mii_data sc_mii; /* MII information */ 727 u_int8_t rl_type; 728 int rl_eecmd_read; 729 int rl_eewidth; 730 void *sc_sdhook; /* shutdownhook */ 731 void *sc_pwrhook; 732 int rl_txthresh; 733 int sc_flags; /* misc flags */ 734 struct rl_chain_data rl_cdata; 735 struct timeout sc_tick_tmo; 736 int if_flags; 737 738 struct rl_list_data rl_ldata; 739 struct mbuf *rl_head; 740 struct mbuf *rl_tail; 741 u_int32_t rl_rxlenmask; 742 int rl_testmode; 743 struct timeout timer_handle; 744 745 int rl_txstart; 746 int rl_link; 747 }; 748 #endif 749 750 /* 751 * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets 752 */ 753 #define RL_IP4CSUMTX_MINLEN 28 754 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 755 /* 756 * XXX 757 * We are allocating pad DMA buffer after RX DMA descs for now 758 * because RL_TX_LIST_SZ(sc) always occupies whole page but 759 * RL_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. 760 */ 761 #define RL_RX_DMAMEM_SZ (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN) 762 #define RL_TXPADOFF RL_RX_LIST_SZ 763 #define RL_TXPADDADDR(sc) \ 764 ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF) 765 766 767 #define RL_ATTACHED 0x00000001 /* attach has succeeded */ 768 #define RL_ENABLED 0x00000002 /* chip is enabled */ 769 #define RL_IS_ENABLED(sc) ((sc)->sc_flags & RL_ENABLED) 770 771 /* 772 * register space access macros 773 */ 774 #define CSR_WRITE_RAW_4(sc, csr, val) \ 775 bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) 776 #define CSR_WRITE_4(sc, csr, val) \ 777 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 778 #define CSR_WRITE_2(sc, csr, val) \ 779 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 780 #define CSR_WRITE_1(sc, csr, val) \ 781 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 782 783 #define CSR_READ_4(sc, csr) \ 784 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 785 #define CSR_READ_2(sc, csr) \ 786 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 787 #define CSR_READ_1(sc, csr) \ 788 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 789 790 #define CSR_SETBIT_1(sc, offset, val) \ 791 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 792 793 #define CSR_CLRBIT_1(sc, offset, val) \ 794 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 795 796 #define CSR_SETBIT_2(sc, offset, val) \ 797 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 798 799 #define CSR_CLRBIT_2(sc, offset, val) \ 800 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 801 802 #define CSR_SETBIT_4(sc, offset, val) \ 803 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 804 805 #define CSR_CLRBIT_4(sc, offset, val) \ 806 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 807 808 #define RL_TIMEOUT 1000 809 810 /* 811 * General constants that are fun to know. 812 * 813 * RealTek PCI vendor ID 814 */ 815 #define RT_VENDORID 0x10EC 816 817 /* 818 * RealTek chip device IDs. 819 */ 820 #define RT_DEVICEID_8129 0x8129 821 #define RT_DEVICEID_8101E 0x8136 822 #define RT_DEVICEID_8138 0x8138 823 #define RT_DEVICEID_8139 0x8139 824 #define RT_DEVICEID_8169SC 0x8167 825 #define RT_DEVICEID_8168 0x8168 826 #define RT_DEVICEID_8169 0x8169 827 #define RT_DEVICEID_8100 0x8100 828 829 /* 830 * Accton PCI vendor ID 831 */ 832 #define ACCTON_VENDORID 0x1113 833 834 /* 835 * Accton MPX 5030/5038 device ID. 836 */ 837 #define ACCTON_DEVICEID_5030 0x1211 838 839 /* 840 * Delta Electronics Vendor ID. 841 */ 842 #define DELTA_VENDORID 0x1500 843 844 /* 845 * Delta device IDs. 846 */ 847 #define DELTA_DEVICEID_8139 0x1360 848 849 /* 850 * Addtron vendor ID. 851 */ 852 #define ADDTRON_VENDORID 0x4033 853 854 /* 855 * Addtron device IDs. 856 */ 857 #define ADDTRON_DEVICEID_8139 0x1360 858 859 /* D-Link Vendor ID */ 860 #define DLINK_VENDORID 0x1186 861 862 /* D-Link device IDs */ 863 #define DLINK_DEVICEID_8139 0x1300 864 #define DLINK_DEVICEID_8139_2 0x1340 865 866 /* Abocom device IDs */ 867 #define ABOCOM_DEVICEID_8139 0xab06 868 869 /* 870 * PCI low memory base and low I/O base register, and 871 * other PCI registers. Note: some are only available on 872 * the 3c905B, in particular those that related to power management. 873 */ 874 875 #define RL_PCI_VENDOR_ID 0x00 876 #define RL_PCI_DEVICE_ID 0x02 877 #define RL_PCI_COMMAND 0x04 878 #define RL_PCI_STATUS 0x06 879 #define RL_PCI_CLASSCODE 0x09 880 #define RL_PCI_LATENCY_TIMER 0x0D 881 #define RL_PCI_HEADER_TYPE 0x0E 882 #define RL_PCI_LOIO 0x10 883 #define RL_PCI_LOMEM 0x14 884 #define RL_PCI_BIOSROM 0x30 885 #define RL_PCI_INTLINE 0x3C 886 #define RL_PCI_INTPIN 0x3D 887 #define RL_PCI_MINGNT 0x3E 888 #define RL_PCI_MINLAT 0x0F 889 #define RL_PCI_RESETOPT 0x48 890 #define RL_PCI_EEPROM_DATA 0x4C 891 892 #define RL_PCI_CAPID 0x50 /* 8 bits */ 893 #define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 894 #define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 895 #define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 896 897 #define RL_PSTATE_MASK 0x0003 898 #define RL_PSTATE_D0 0x0000 899 #define RL_PSTATE_D1 0x0002 900 #define RL_PSTATE_D2 0x0002 901 #define RL_PSTATE_D3 0x0003 902 #define RL_PME_EN 0x0010 903 #define RL_PME_STATUS 0x8000 904 905 #if 0 906 extern int rl_attach(struct rl_softc *); 907 extern int rl_detach(struct rl_softc *); 908 extern int rl_intr(void *); 909 extern void rl_setmulti(struct rl_softc *); 910 #endif 911 912 #endif /* RTL81X9REG_H */ 913