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/dports/games/bzflag-server/bzflag-2.4.22/package/
H A DMakefile.am15 RMR = del.exe /F /Q /S macro
25 RMR = $(RM) -r macro
75 -$(RMR) $(RPMDIR) $(TMPROOT)
126 $(RMR) $(RPMDIR) $(TMPROOT) newspec
/dports/games/bzflag/bzflag-2.4.22/package/
H A DMakefile.am15 RMR = del.exe /F /Q /S macro
25 RMR = $(RM) -r macro
75 -$(RMR) $(RPMDIR) $(TMPROOT)
126 $(RMR) $(RPMDIR) $(TMPROOT) newspec
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-sunxi/
H A Drmr_switch.S2 @ ARMv8 RMR reset sequence on Allwinner SoCs.
8 @ (RMR), which triggers a warm-reset of a core and can request to switch
42 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
44 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register

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