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Searched refs:RP_CFG_ADDR (Results 1 – 25 of 62) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/pci/
H A Dpcie_intel_fpga.c41 #define RP_CFG_ADDR(pcie, reg) \ macro
44 readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
118 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
235 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()

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