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Searched refs:RREG32_UVD_CTX (Results 1 – 25 of 30) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c368 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v3_1_start()
603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
612 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
H A Duvd_v4_2.c300 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v4_2_start()
584 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
593 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
H A Duvd_v5_0.c744 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
753 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
H A Damdgpu_cgs.c68 return RREG32_UVD_CTX(index); in amdgpu_cgs_read_ind_register()
H A Duvd_v6_0.c1411 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1420 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
H A Damdgpu.h1168 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c368 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v3_1_start()
603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
612 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
H A Duvd_v4_2.c300 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v4_2_start()
584 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
593 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
H A Duvd_v5_0.c744 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
753 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
H A Damdgpu_cgs.c68 return RREG32_UVD_CTX(index); in amdgpu_cgs_read_ind_register()
H A Duvd_v6_0.c1411 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1420 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
H A Damdgpu.h1168 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c300 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v4_2_start()
584 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
593 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
H A Duvd_v3_1.c368 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v3_1_start()
603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
612 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
H A Duvd_v5_0.c744 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
753 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
H A Damdgpu_cgs.c68 return RREG32_UVD_CTX(index); in amdgpu_cgs_read_ind_register()
H A Duvd_v6_0.c1411 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1420 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
H A Damdgpu.h1168 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsi.c5191 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5203 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
H A Dradeon.h2460 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dsi.c5452 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5464 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
H A Dradeon.h2529 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dsi.c5452 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5464 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dsi.c5452 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
5464 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
H A Dradeon.h2529 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) macro

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