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Searched refs:RS600_EFFECTIVE_L2_CACHE_SIZE (Results 1 – 8 of 8) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dr500_reg.h202 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
H A Dradeon_drv.h627 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
H A Dradeon_cp.c991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | in rs600_set_igpgart()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dr500_reg.h202 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dr500_reg.h202 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dr500_reg.h202 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/
H A Dradeon_drv.h712 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) macro
H A Dradeon_cp.c855 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | in rs600_set_igpgart()