/dports/games/libretro-uae/libretro-uae-8333daa/sources/src/ |
H A D | cdrom.c | 119 #define RS_L12_BITS 8 macro 145 if (sum >= ((1 << RS_L12_BITS)-1)) in encode_L2_Q() 146 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 149 if (sum >= ((1 << RS_L12_BITS)-1)) in encode_L2_Q() 150 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 159 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 163 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 187 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() 191 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() 200 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() [all …]
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/dports/emulators/fs-uae/fs-uae-3.1.35/src/ |
H A D | cdrom.cpp | 119 #define RS_L12_BITS 8 macro 145 if (sum >= ((1 << RS_L12_BITS)-1)) in encode_L2_Q() 146 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 149 if (sum >= ((1 << RS_L12_BITS)-1)) in encode_L2_Q() 150 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 159 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 163 sum -= (1 << RS_L12_BITS)-1; in encode_L2_Q() 187 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() 191 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() 200 sum -= (1 << RS_L12_BITS)-1; in encode_L2_P() [all …]
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/dports/devel/sunpromake/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/devel/smake/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/devel/schilybase/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/net/rscsi/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/archivers/star/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/sysutils/cdrkit/cdrkit-1.1.11/libedc/ |
H A D | edc_ecc.c | 338 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 339 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 340 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 341 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 364 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 365 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 366 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 367 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P()
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H A D | ecc.h | 36 #define RS_L12_BITS 8 macro
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/dports/sysutils/cdrtools/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/editors/ved/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/sysutils/genisoimage/cdrkit-1.1.11/libedc/ |
H A D | edc_ecc.c | 338 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 339 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 340 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 341 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_Q() 364 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 365 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 366 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P() 367 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; in encode_L1_P()
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H A D | ecc.h | 36 #define RS_L12_BITS 8 in ParallelLoopGeneratorGOMP()
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/dports/devel/sccs/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/sysutils/schilyutils/schily-2021-09-18/libedc/ |
H A D | edc_ecc.c | 357 Q[0] ^= rs_l12_alog[(base+AQ[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 358 Q[1] ^= rs_l12_alog[(base+AQ[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 359 Q[2] ^= rs_l12_alog[(base+AQ[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 360 Q[3] ^= rs_l12_alog[(base+AQ[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 385 P[0] ^= rs_l12_alog[(base+AP[0][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 386 P[1] ^= rs_l12_alog[(base+AP[1][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 387 P[2] ^= rs_l12_alog[(base+AP[2][i]) % (unsigned)((1 << RS_L12_BITS)-1)]; 388 P[3] ^= rs_l12_alog[(base+AP[3][i]) % (unsigned)((1 << RS_L12_BITS)-1)];
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H A D | ecc.h | 23 #define RS_L12_BITS 8 macro
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/dports/multimedia/vcdimager/vcdimager-2.0.1/lib/ |
H A D | sector_private.h | 25 #define RS_L12_BITS 8 macro
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