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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/
H A Dcpu.c113 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
123 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_09_1_cpu_init()
132 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_10_0_cpu_init()
141 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32imacu_nommu_cpu_init()
151 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_09_1_cpu_init()
160 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_10_0_cpu_init()
169 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64imacu_nommu_cpu_init()
/dports/finance/sql-ledger/sql-ledger/locale/ja/
H A Darapprn13 'RVC missing!' => 'RVCが必要です',
H A Dio96 'RVC missing!' => 'RVCが必要です',
/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dcpu.c116 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
133 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_09_1_cpu_init()
143 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_10_0_cpu_init()
153 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32imacu_nommu_cpu_init()
171 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_09_1_cpu_init()
181 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_10_0_cpu_init()
191 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64imacu_nommu_cpu_init()
404 target_misa |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dcpu.c116 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
133 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_09_1_cpu_init()
143 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_10_0_cpu_init()
153 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32imacu_nommu_cpu_init()
171 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_09_1_cpu_init()
181 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_10_0_cpu_init()
191 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64imacu_nommu_cpu_init()
404 target_misa |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dcpu.c143 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
145 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
161 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
168 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
183 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
190 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
198 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
514 ext |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dcpu.c124 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
141 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_09_1_cpu_init()
151 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_10_0_cpu_init()
161 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32imacu_nommu_cpu_init()
179 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_09_1_cpu_init()
189 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_10_0_cpu_init()
199 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64imacu_nommu_cpu_init()
449 target_misa |= RVC; in riscv_cpu_realize()
/dports/finance/sql-ledger/sql-ledger/locale/mx/
H A Darapprn13 'RVC missing!' => '¡Falta RVC!',
/dports/finance/sql-ledger/sql-ledger/locale/sk/
H A Darapprn13 'RVC missing!' => 'RVC chýba !',
/dports/finance/sql-ledger/sql-ledger/locale/fr/
H A Darapprn13 'RVC missing!' => 'RVC manquant',
/dports/finance/sql-ledger/sql-ledger/locale/nl/
H A Darapprn13 'RVC missing!' => 'RVC ontbreekt!',
/dports/finance/sql-ledger/sql-ledger/locale/se/
H A Darapprn13 'RVC missing!' => 'RVC saknas',
/dports/finance/sql-ledger/sql-ledger/locale/cafr/
H A Darapprn13 'RVC missing!' => 'RVC manquant',
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dcpu.c156 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
158 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
174 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
181 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
196 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
203 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
211 set_misa(env, RV32 | RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
220 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
488 target_misa |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/
H A Dcpu.c150 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
165 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
172 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
187 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
194 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
202 set_misa(env, RV32 | RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
210 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
465 target_misa |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dcheri-archspecific.h91 unsigned min_base_alignment = riscv_has_ext(env, RVC) ? 2 : 4; in validate_cjalr_target()
96 if (!riscv_has_ext(env, RVC) && (new_addr & 0x2)) { in validate_cjalr_target()
H A Dcpu.c145 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
162 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_09_1_cpu_init()
172 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32gcsu_priv1_10_0_cpu_init()
182 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); in rv32imacu_nommu_cpu_init()
200 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_09_1_cpu_init()
210 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64gcsu_priv1_10_0_cpu_init()
220 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); in rv64imacu_nommu_cpu_init()
696 target_misa |= RVC; in riscv_cpu_realize()
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/
H A Dcpu.c141 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
155 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rvxx_sifive_u_cpu_init()
162 set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); in rvxx_sifive_e_cpu_init()
172 set_misa(env, RV32 | RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
180 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
433 target_misa |= RVC; in riscv_cpu_realize()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/RISCV/
H A Drv32c-invalid.s25 c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructio…
27 c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructi…
33 c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
58 c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/RISCV/
H A Drv32c-invalid.s25 c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructio…
27 c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructi…
33 c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
58 c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions

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