/dports/devel/gdb761/gdb-7.6.1/sim/bfin/ |
H A D | dv-bfin_emac.h | 44 #define RXDWA (1 << 1) macro
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/dports/devel/avr-gdb/gdb-7.3.1/sim/bfin/ |
H A D | dv-bfin_emac.h | 47 #define RXDWA (1 << 1) macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/bits/ |
H A D | emac.h | 107 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/ |
H A D | defBF537.h | 317 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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H A D | defBF516.h | 416 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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H A D | defBF518.h | 442 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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H A D | defBF527.h | 327 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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H A D | defBF526.h | 327 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ macro
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/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/net/ |
H A D | bfin_mac.c | 236 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/net/ |
H A D | bfin_mac.c | 264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
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