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Searched refs:R_8 (Results 1 – 25 of 134) sorted by relevance

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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Ds390-opc.c48 #define R_8 1 /* GPR starting at position 8 */ macro
231 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
232 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
233 #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
234 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
235 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
236 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
237 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
239 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
240 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
[all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Ds390-opc.c48 #define R_8 1 /* GPR starting at position 8 */ macro
288 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
289 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
290 #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */
291 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
292 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
293 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
294 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
296 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
297 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Ds390-opc.c45 #define R_8 1 /* GPR starting at position 8 */ macro
184 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
186 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
188 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
189 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
191 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
192 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
193 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
215 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
216 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
[all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Ds390-opc.c45 #define R_8 1 /* GPR starting at position 8 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
179 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
182 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
183 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
184 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
205 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c45 #define R_8 1 /* GPR starting at position 8 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
179 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
182 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
183 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
184 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
205 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c45 #define R_8 1 /* GPR starting at position 8 */ macro
177 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
179 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
182 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
183 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
184 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
205 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
206 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
209 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
210 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
300 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
301 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
303 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
304 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
305 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
306 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
308 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
309 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
310 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
300 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
301 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
303 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
304 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
305 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
306 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
308 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
309 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
310 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
308 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
309 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
310 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
312 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
313 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
314 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
308 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
309 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
310 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
312 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
313 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
314 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
308 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
309 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
310 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
312 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
313 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
314 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A Ds390-opc.c47 #define R_8 1 /* GPR starting at position 8 */ macro
304 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
305 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */
307 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */
308 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */
309 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */
310 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */
312 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */
313 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */
314 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c105 R_8, /* GPR starting at position 8 */ enumerator
167 [R_8] = { 4, 8, OPERAND_GPR },
210 [INSTR_RIL_RI] = { R_8, I32_16, 0, 0, 0, 0 },
211 [INSTR_RIL_RP] = { R_8, J32_16, 0, 0, 0, 0 },
212 [INSTR_RIL_RU] = { R_8, U32_16, 0, 0, 0, 0 },
216 [INSTR_RI_RI] = { R_8, I16_16, 0, 0, 0, 0 },
217 [INSTR_RI_RP] = { R_8, J16_16, 0, 0, 0, 0 },
218 [INSTR_RI_RU] = { R_8, U16_16, 0, 0, 0, 0 },
251 [INSTR_RR_R0] = { R_8, 0, 0, 0, 0, 0 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c105 R_8, /* GPR starting at position 8 */ enumerator
167 [R_8] = { 4, 8, OPERAND_GPR },
210 [INSTR_RIL_RI] = { R_8, I32_16, 0, 0, 0, 0 },
211 [INSTR_RIL_RP] = { R_8, J32_16, 0, 0, 0, 0 },
212 [INSTR_RIL_RU] = { R_8, U32_16, 0, 0, 0, 0 },
216 [INSTR_RI_RI] = { R_8, I16_16, 0, 0, 0, 0 },
217 [INSTR_RI_RP] = { R_8, J16_16, 0, 0, 0, 0 },
218 [INSTR_RI_RU] = { R_8, U16_16, 0, 0, 0, 0 },
251 [INSTR_RR_R0] = { R_8, 0, 0, 0, 0, 0 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c105 R_8, /* GPR starting at position 8 */ enumerator
167 [R_8] = { 4, 8, OPERAND_GPR },
210 [INSTR_RIL_RI] = { R_8, I32_16, 0, 0, 0, 0 },
211 [INSTR_RIL_RP] = { R_8, J32_16, 0, 0, 0, 0 },
212 [INSTR_RIL_RU] = { R_8, U32_16, 0, 0, 0, 0 },
216 [INSTR_RI_RI] = { R_8, I16_16, 0, 0, 0, 0 },
217 [INSTR_RI_RP] = { R_8, J16_16, 0, 0, 0, 0 },
218 [INSTR_RI_RU] = { R_8, U16_16, 0, 0, 0, 0 },
251 [INSTR_RR_R0] = { R_8, 0, 0, 0, 0, 0 },
252 [INSTR_RR_RR] = { R_8, R_12, 0, 0, 0, 0 },
[all …]
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/ui/gfx/
H A Dbuffer_format_util.cc14 const BufferFormat kBufferFormats[] = {BufferFormat::R_8,
54 case BufferFormat::R_8: in AlphaBitsForBufferFormat()
71 case BufferFormat::R_8: in NumberOfPlanesForLinearBufferFormat()
96 case BufferFormat::R_8: in SubsamplingFactorForBufferFormat()
138 case BufferFormat::R_8: in RowSizeForBufferFormatChecked()
222 case BufferFormat::R_8: in BufferOffsetForBufferFormat()
260 case BufferFormat::R_8: in BufferFormatToString()
/dports/www/chromium-legacy/chromium-88.0.4324.182/ui/gfx/
H A Dbuffer_format_util.cc15 const BufferFormat kBufferFormats[] = {BufferFormat::R_8,
55 case BufferFormat::R_8: in AlphaBitsForBufferFormat()
72 case BufferFormat::R_8: in NumberOfPlanesForLinearBufferFormat()
97 case BufferFormat::R_8: in SubsamplingFactorForBufferFormat()
139 case BufferFormat::R_8: in RowSizeForBufferFormatChecked()
223 case BufferFormat::R_8: in BufferOffsetForBufferFormat()
261 case BufferFormat::R_8: in BufferFormatToString()
/dports/math/apache-commons-math/commons-math3-3.6.1-src/src/test/java/org/apache/commons/math3/stat/descriptive/rank/
H A DPercentileTest.java251 …{ Percentile.EstimationType.R_7, 0.25 }, { Percentile.EstimationType.R_8, 0d }, {Percentile.Estima… in testAllTechniquesLowPercentile()
266 …{ Percentile.EstimationType.R_8, 1.41667 }, { Percentile.EstimationType.R_9, 1.43750 } }, 25d, 1.0… in checkAllTechniquesPercentile()
271 …{ Percentile.EstimationType.R_8, 3.58333 },{ Percentile.EstimationType.R_9, 3.56250} }, 75d, 1.0e-… in checkAllTechniquesPercentile()
276 … { Percentile.EstimationType.R_8, 2.5 },{ Percentile.EstimationType.R_9, 2.5 } }, 50d, 1.0e-05); in checkAllTechniquesPercentile()
353 … { Percentile.EstimationType.R_7, 8.8100 }, { Percentile.EstimationType.R_8, 8.4700 }, in testAllTechniques5()
469 …{ Percentile.EstimationType.R_7, 2.0 }, { Percentile.EstimationType.R_8, 2.0 }, { Percentile.Estim… in testAllTechniquesSpecialValues()
479 … { Percentile.EstimationType.R_8, 2.0 }, { Percentile.EstimationType.R_9, 2.0 } }, 50d, 0d); in testAllTechniquesSpecialValues()
495 { Percentile.EstimationType.R_8, Double.POSITIVE_INFINITY }, in testAllTechniquesSpecialValues()
503 … { Percentile.EstimationType.R_8, 1.0 }, { Percentile.EstimationType.R_9, 1.0 },}, 50d, 0d); in testAllTechniquesSpecialValues()
570 …{ Percentile.EstimationType.R_7, 19.555 }, { Percentile.EstimationType.R_8, 20.460 },{ Percentile.… in testAllTechniquesEvaluation()
[all …]
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Ds390.c483 #define R_8 1 /* GPR starting at position 8 */ macro
643 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
645 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
647 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
648 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
809 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
812 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
815 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
817 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
821 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Ds390.c482 #define R_8 1 /* GPR starting at position 8 */ macro
642 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
644 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
646 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
647 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
808 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
811 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
814 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
816 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
820 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
[all …]

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