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Searched refs:R_CR (Results 1 – 25 of 67) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/hw/timer/
H A Dlm32_timer.c39 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu60/qemu-6.0.0/hw/timer/
H A Dlm32_timer.c40 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/timer/
H A Dlm32_timer.c39 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/timer/
H A Dlm32_timer.c37 R_CR, enumerator
75 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
89 case R_CR: in timer_read()
118 case R_CR: in timer_write()
119 s->regs[R_CR] = value; in timer_write()
120 if (s->regs[R_CR] & CR_START) { in timer_write()
123 if (s->regs[R_CR] & CR_STOP) { in timer_write()
161 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu5/qemu-5.2.0/hw/timer/
H A Dlm32_timer.c40 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/timer/
H A Dlm32_timer.c39 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/timer/
H A Dlm32_timer.c39 R_CR, enumerator
76 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); in timer_update_irq()
90 case R_CR: in timer_read()
119 case R_CR: in timer_write()
121 s->regs[R_CR] = value; in timer_write()
122 if (s->regs[R_CR] & CR_START) { in timer_write()
125 if (s->regs[R_CR] & CR_STOP) { in timer_write()
166 if (s->regs[R_CR] & CR_CONT) { in timer_hit()
/dports/emulators/qemu42/qemu-4.2.1/hw/char/
H A Dcadence_uart.c102 #define R_CR (0x00/4) macro
239 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
243 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
249 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
260 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
317 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
365 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
430 case R_CR: in uart_write()
469 s->r[R_CR] = 0x00000128; in cadence_uart_reset()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/char/
H A Dcadence_uart.c99 #define R_CR (0x00/4) macro
236 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
240 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
244 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
246 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
257 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
314 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
362 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
427 case R_CR: in uart_write()
466 s->r[R_CR] = 0x00000128; in cadence_uart_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/char/
H A Dcadence_uart.c102 #define R_CR (0x00/4) macro
239 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
243 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
249 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
260 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
317 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
365 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
430 case R_CR: in uart_write()
469 s->r[R_CR] = 0x00000128; in cadence_uart_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/char/
H A Dcadence_uart.c102 #define R_CR (0x00/4)
239 if (s->r[R_CR] & UART_CR_TXRST) {
243 if (s->r[R_CR] & UART_CR_RXRST) {
247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
249 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
260 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
317 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
365 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
430 case R_CR:
469 s->r[R_CR] = 0x00000128;
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/char/
H A Dcadence_uart.c102 #define R_CR (0x00/4) macro
239 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
243 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
249 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
260 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
317 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
365 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
430 case R_CR: in uart_write()
469 s->r[R_CR] = 0x00000128; in cadence_uart_reset()
/dports/emulators/qemu/qemu-6.2.0/hw/char/
H A Dcadence_uart.c105 #define R_CR (0x00/4) macro
262 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
266 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
270 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
272 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
283 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
340 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
395 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
467 case R_CR: in uart_write()
517 s->r[R_CR] = 0x00000128; in cadence_uart_reset_init()
/dports/emulators/qemu60/qemu-6.0.0/hw/char/
H A Dcadence_uart.c105 #define R_CR (0x00/4) macro
252 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
256 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
260 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
262 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
273 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
330 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
388 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
453 case R_CR: in uart_write()
492 s->r[R_CR] = 0x00000128; in cadence_uart_reset_init()
/dports/emulators/qemu5/qemu-5.2.0/hw/char/
H A Dcadence_uart.c104 #define R_CR (0x00/4) macro
251 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
255 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
259 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
261 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
272 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
329 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
387 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
452 case R_CR: in uart_write()
491 s->r[R_CR] = 0x00000128; in cadence_uart_reset_init()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/char/
H A Dcadence_uart.c105 #define R_CR (0x00/4) macro
262 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
266 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
270 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
272 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
283 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
340 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
395 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
467 case R_CR: in uart_write()
517 s->r[R_CR] = 0x00000128; in cadence_uart_reset_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h401 #define R_CR 0x00040000 /* CRC Error */ macro
404 #define R_ERROR (R_NO | R_AB | R_CR | R_OV)
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h401 #define R_CR 0x00040000 /* CRC Error */ macro
404 #define R_ERROR (R_NO | R_AB | R_CR | R_OV)
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h401 #define R_CR 0x00040000 /* CRC Error */ macro
404 #define R_ERROR (R_NO | R_AB | R_CR | R_OV)
/dports/multimedia/libv4l/linux-5.13-rc2/include/soc/fsl/qe/
H A Ducc_slow.h68 #define R_CR 0x00040000 /* CRC Error */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/soc/fsl/qe/
H A Ducc_slow.h68 #define R_CR 0x00040000 /* CRC Error */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/soc/fsl/qe/
H A Ducc_slow.h68 #define R_CR 0x00040000 /* CRC Error */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/freescale/
H A Ducc_geth.h821 #define R_CR 0x00040000 /* CRC error. */ macro
830 #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/freescale/
H A Ducc_geth.h821 #define R_CR 0x00040000 /* CRC error. */ macro
830 #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/freescale/
H A Ducc_geth.h821 #define R_CR 0x00040000 /* CRC error. */ macro
830 #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \

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