/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/lib/ |
H A D | cache_init.S | 105 #define R_L2_LINE s6 macro 117 move R_L2_LINE, zero 150 ext R_L2_LINE, t1, \ 152 beqz R_L2_LINE, l2_probe_done 154 sllv R_L2_LINE, t2, R_L2_LINE 158 mul R_L2_SIZE, R_L2_LINE, t2 193 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 194 beqz R_L2_LINE, l2_probe_done 196 sllv R_L2_LINE, t1, R_L2_LINE 201 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/lib/ |
H A D | cache_init.S | 105 #define R_L2_LINE s6 macro 117 move R_L2_LINE, zero 150 ext R_L2_LINE, t1, \ 152 beqz R_L2_LINE, l2_probe_done 154 sllv R_L2_LINE, t2, R_L2_LINE 158 mul R_L2_SIZE, R_L2_LINE, t2 193 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 194 beqz R_L2_LINE, l2_probe_done 196 sllv R_L2_LINE, t1, R_L2_LINE 201 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/lib/ |
H A D | cache_init.S | 105 #define R_L2_LINE s6 macro 117 move R_L2_LINE, zero 150 ext R_L2_LINE, t1, \ 152 beqz R_L2_LINE, l2_probe_done 154 sllv R_L2_LINE, t2, R_L2_LINE 158 mul R_L2_SIZE, R_L2_LINE, t2 193 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 194 beqz R_L2_LINE, l2_probe_done 196 sllv R_L2_LINE, t1, R_L2_LINE 201 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/lib/ |
H A D | cache_init.S | 105 #define R_L2_LINE s6 macro 117 move R_L2_LINE, zero 150 ext R_L2_LINE, t1, \ 152 beqz R_L2_LINE, l2_probe_done 154 sllv R_L2_LINE, t2, R_L2_LINE 158 mul R_L2_SIZE, R_L2_LINE, t2 193 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 194 beqz R_L2_LINE, l2_probe_done 196 sllv R_L2_LINE, t1, R_L2_LINE 201 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/mips/lib/ |
H A D | cache_init.S | 120 #define R_L2_LINE s6 macro 132 move R_L2_LINE, zero 165 ext R_L2_LINE, t1, \ 167 beqz R_L2_LINE, l2_probe_done 169 sllv R_L2_LINE, t2, R_L2_LINE 173 mul R_L2_SIZE, R_L2_LINE, t2 208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF 209 beqz R_L2_LINE, l2_probe_done 211 sllv R_L2_LINE, t1, R_L2_LINE 216 mul R_L2_SIZE, R_L2_LINE, t1 [all …]
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