/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 635 RegisterSubReg DefR(MD); in visitPHI() 662 RegisterSubReg UseR(SO); in visitPHI() 705 RegisterSubReg DefR(MO); in visitNonBranch() 1943 RegisterSubReg DefR(MD); in evaluate() 2301 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 635 RegisterSubReg DefR(MD); in visitPHI() 662 RegisterSubReg UseR(SO); in visitPHI() 705 RegisterSubReg DefR(MO); in visitNonBranch() 1943 RegisterSubReg DefR(MD); in evaluate() 2301 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 635 RegisterSubReg DefR(MD); in visitPHI() 662 RegisterSubReg UseR(SO); in visitPHI() 705 RegisterSubReg DefR(MO); in visitNonBranch() 1937 RegisterSubReg DefR(MD); in evaluate() 2295 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 364 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 381 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 386 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 391 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 634 RegisterSubReg DefR(MD); in visitPHI() 661 RegisterSubReg UseR(SO); in visitPHI() 704 RegisterSubReg DefR(MO); in visitNonBranch() 1942 RegisterSubReg DefR(MD); in evaluate() 2300 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 364 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 381 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 386 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 391 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 634 RegisterSubReg DefR(MD); in visitPHI() 661 RegisterSubReg UseR(SO); in visitPHI() 704 RegisterSubReg DefR(MO); in visitNonBranch() 1942 RegisterSubReg DefR(MD); in evaluate() 2300 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 364 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 381 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 386 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 391 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 634 RegisterSubReg DefR(MD); in visitPHI() 661 RegisterSubReg UseR(SO); in visitPHI() 704 RegisterSubReg DefR(MO); in visitNonBranch() 1942 RegisterSubReg DefR(MD); in evaluate() 2300 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 635 RegisterSubReg DefR(MD); in visitPHI() 662 RegisterSubReg UseR(SO); in visitPHI() 705 RegisterSubReg DefR(MO); in visitNonBranch() 1943 RegisterSubReg DefR(MD); in evaluate() 2301 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 72 RegisterSubReg Reg; 105 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 121 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 245 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 280 return RegisterSubReg(NewPR); in getPredRegFor() 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 378 RegisterSubReg Reg(MO); in convertToPredForm() 416 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 635 RegisterSubReg DefR(MD); in visitPHI() 662 RegisterSubReg UseR(SO); in visitPHI() 705 RegisterSubReg DefR(MO); in visitNonBranch() 1937 RegisterSubReg DefR(MD); in evaluate() 2295 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 364 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 381 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 386 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 391 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 634 RegisterSubReg DefR(MD); in visitPHI() 661 RegisterSubReg UseR(SO); in visitPHI() 704 RegisterSubReg DefR(MO); in visitNonBranch() 1942 RegisterSubReg DefR(MD); in evaluate() 2300 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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H A D | HexagonConstPropagation.cpp | 85 struct RegisterSubReg { struct 364 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, 381 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 386 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 391 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, 634 RegisterSubReg DefR(MD); in visitPHI() 661 RegisterSubReg UseR(SO); in visitPHI() 704 RegisterSubReg DefR(MO); in visitNonBranch() 1942 RegisterSubReg DefR(MD); in evaluate() 2300 RegisterSubReg PR(MD); in evaluate() [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 struct RegisterSubReg { struct 73 RegisterSubReg Reg; 106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 246 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 281 return RegisterSubReg(NewPR); in getPredRegFor() 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 379 RegisterSubReg Reg(MO); in convertToPredForm() 417 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 49 struct RegisterSubReg { struct 71 RegisterSubReg Reg; 104 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>; 120 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg); 244 RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) { in getPredRegFor() 279 return RegisterSubReg(NewPR); in getPredRegFor() 322 std::queue<RegisterSubReg> WorkQ; in isScalarPred() 326 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 377 RegisterSubReg Reg(MO); in convertToPredForm() 415 RegisterSubReg OutR(Op0); in convertToPredForm() [all …]
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