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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h69 uint8_t RsrcIndex; member
H A DMIMGInstructions.td912 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
927 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1694 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1076 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1091 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1713 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1076 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1091 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1713 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td914 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
929 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1683 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1076 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1091 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1713 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1086 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1101 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1076 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1091 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1713 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td914 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
929 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",
H A DAMDGPUInstructionSelector.cpp1683 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg()); in selectImageIntrinsic()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.h68 uint8_t RsrcIndex; member
H A DMIMGInstructions.td1076 bits<8> RsrcIndex = DimEval.RsrcArgIndex;
1091 "RsrcIndex", "SampIndex", "UnormIndex", "TexFailCtrlIndex", "CachePolicyIndex",

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