1 /***************************************************************************
2  *   Copyright (C) 2004, 2005 by Simtec Electronics                        *
3  *   linux@simtec.co.uk                                                    *
4  *   http://www.simtec.co.uk/products/SWLINUX/                             *
5  *                                                                         *
6  *   This program is free software; you can redistribute it and/or modify  *
7  *   it under the terms of the GNU General Public License as published by  *
8  *   the Free Software Foundation; version 2 of the License.               *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
17  ***************************************************************************/
18 
19 /*
20  * S3C2410 NAND register definitions
21  */
22 
23 #ifndef OPENOCD_FLASH_NAND_S3C24XX_REGS_H
24 #define OPENOCD_FLASH_NAND_S3C24XX_REGS_H
25 
26 #define S3C2410_NFREG(x) (x)
27 
28 #define S3C2410_NFCONF  S3C2410_NFREG(0x00)
29 #define S3C2410_NFCMD   S3C2410_NFREG(0x04)
30 #define S3C2410_NFADDR  S3C2410_NFREG(0x08)
31 #define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
32 #define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
33 #define S3C2410_NFECC   S3C2410_NFREG(0x14)
34 
35 #define S3C2440_NFCONT   S3C2410_NFREG(0x04)
36 #define S3C2440_NFCMD    S3C2410_NFREG(0x08)
37 #define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
38 #define S3C2440_NFDATA   S3C2410_NFREG(0x10)
39 #define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
40 #define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
41 #define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
42 #define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
43 #define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
44 #define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
45 #define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
46 #define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
47 #define S3C2440_NFSECC   S3C2410_NFREG(0x34)
48 #define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
49 #define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
50 
51 #define S3C2412_NFSBLK		S3C2410_NFREG(0x20)
52 #define S3C2412_NFEBLK		S3C2410_NFREG(0x24)
53 #define S3C2412_NFSTAT		S3C2410_NFREG(0x28)
54 #define S3C2412_NFMECC_ERR0	S3C2410_NFREG(0x2C)
55 #define S3C2412_NFMECC_ERR1	S3C2410_NFREG(0x30)
56 #define S3C2412_NFMECC0		S3C2410_NFREG(0x34)
57 #define S3C2412_NFMECC1		S3C2410_NFREG(0x38)
58 #define S3C2412_NFSECC		S3C2410_NFREG(0x3C)
59 
60 #define S3C2410_NFCONF_EN          (1 << 15)
61 #define S3C2410_NFCONF_512BYTE     (1 << 14)
62 #define S3C2410_NFCONF_4STEP       (1 << 13)
63 #define S3C2410_NFCONF_INITECC     (1 << 12)
64 #define S3C2410_NFCONF_nFCE        (1 << 11)
65 #define S3C2410_NFCONF_TACLS(x)    ((x) << 8)
66 #define S3C2410_NFCONF_TWRPH0(x)   ((x) << 4)
67 #define S3C2410_NFCONF_TWRPH1(x)   ((x) << 0)
68 
69 #define S3C2410_NFSTAT_BUSY        (1 << 0)
70 
71 #define S3C2440_NFCONF_BUSWIDTH_8	(0 << 0)
72 #define S3C2440_NFCONF_BUSWIDTH_16	(1 << 0)
73 #define S3C2440_NFCONF_ADVFLASH		(1 << 3)
74 #define S3C2440_NFCONF_TACLS(x)		((x) << 12)
75 #define S3C2440_NFCONF_TWRPH0(x)	((x) << 8)
76 #define S3C2440_NFCONF_TWRPH1(x)	((x) << 4)
77 
78 #define S3C2440_NFCONT_LOCKTIGHT	(1 << 13)
79 #define S3C2440_NFCONT_SOFTLOCK		(1 << 12)
80 #define S3C2440_NFCONT_ILLEGALACC_EN	(1 << 10)
81 #define S3C2440_NFCONT_RNBINT_EN	(1 << 9)
82 #define S3C2440_NFCONT_RN_FALLING	(1 << 8)
83 #define S3C2440_NFCONT_SPARE_ECCLOCK	(1 << 6)
84 #define S3C2440_NFCONT_MAIN_ECCLOCK	(1 << 5)
85 #define S3C2440_NFCONT_INITECC		(1 << 4)
86 #define S3C2440_NFCONT_nFCE			(1 << 1)
87 #define S3C2440_NFCONT_ENABLE		(1 << 0)
88 
89 #define S3C2440_NFSTAT_READY		(1 << 0)
90 #define S3C2440_NFSTAT_nCE			(1 << 1)
91 #define S3C2440_NFSTAT_RnB_CHANGE	(1 << 2)
92 #define S3C2440_NFSTAT_ILLEGAL_ACCESS	(1 << 3)
93 
94 #define S3C2412_NFCONF_NANDBOOT		(1 << 31)
95 #define S3C2412_NFCONF_ECCCLKCON	(1 << 30)
96 #define S3C2412_NFCONF_ECC_MLC		(1 << 24)
97 #define S3C2412_NFCONF_TACLS_MASK	(7 << 12)	/* 1 extra bit of Tacls */
98 
99 #define S3C2412_NFCONT_ECC4_DIRWR	(1 << 18)
100 #define S3C2412_NFCONT_LOCKTIGHT	(1 << 17)
101 #define S3C2412_NFCONT_SOFTLOCK		(1 << 16)
102 #define S3C2412_NFCONT_ECC4_ENCINT	(1 << 13)
103 #define S3C2412_NFCONT_ECC4_DECINT	(1 << 12)
104 #define S3C2412_NFCONT_MAIN_ECC_LOCK	(1 << 7)
105 #define S3C2412_NFCONT_INIT_MAIN_ECC	(1 << 5)
106 #define S3C2412_NFCONT_nFCE1		(1 << 2)
107 #define S3C2412_NFCONT_nFCE0		(1 << 1)
108 
109 #define S3C2412_NFSTAT_ECC_ENCDONE	(1 << 7)
110 #define S3C2412_NFSTAT_ECC_DECDONE	(1 << 6)
111 #define S3C2412_NFSTAT_ILLEGAL_ACCESS	(1 << 5)
112 #define S3C2412_NFSTAT_RnB_CHANGE	(1 << 4)
113 #define S3C2412_NFSTAT_nFCE1		(1 << 3)
114 #define S3C2412_NFSTAT_nFCE0		(1 << 2)
115 #define S3C2412_NFSTAT_Res1			(1 << 1)
116 #define S3C2412_NFSTAT_READY		(1 << 0)
117 
118 #define S3C2412_NFECCERR_SERRDATA(x)	(((x) >> 21) & 0xf)
119 #define S3C2412_NFECCERR_SERRBIT(x)		(((x) >> 18) & 0x7)
120 #define S3C2412_NFECCERR_MERRDATA(x)	(((x) >> 7) & 0x3ff)
121 #define S3C2412_NFECCERR_MERRBIT(x)		(((x) >> 4) & 0x7)
122 #define S3C2412_NFECCERR_SPARE_ERR(x)	(((x) >> 2) & 0x3)
123 #define S3C2412_NFECCERR_MAIN_ERR(x)	(((x) >> 2) & 0x3)
124 #define S3C2412_NFECCERR_NONE		(0)
125 #define S3C2412_NFECCERR_1BIT		(1)
126 #define S3C2412_NFECCERR_MULTIBIT	(2)
127 #define S3C2412_NFECCERR_ECCAREA	(3)
128 
129 #endif /* OPENOCD_FLASH_NAND_S3C24XX_REGS_H */
130