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Searched refs:SBTMSLOW_CLOCK (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/
H A Db44.c171 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
172 == SBTMSLOW_CLOCK); in ssb_is_core_up()
204 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
208 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
220 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
236 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h288 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro
/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/
H A Db44.c172 return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK)) in ssb_is_core_up()
173 == SBTMSLOW_CLOCK); in ssb_is_core_up()
205 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK)); in ssb_core_disable()
209 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK | in ssb_core_disable()
221 const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET); in ssb_core_reset()
237 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC)); in ssb_core_reset()
240 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK)); in ssb_core_reset()
H A Db44.h287 #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */ macro