1 /**************************************************************************************\ 2 * * 3 * The Lisa Emulator Project V1.2.6 DEV 2007.12.04 * 4 * http://lisaem.sunder.net * 5 * * 6 * Copyright (C) 1998, 2007 Ray A. Arachelian * 7 * All Rights Reserved * 8 * * 9 * This program is free software; you can redistribute it and/or * 10 * modify it under the terms of the GNU General Public License * 11 * as published by the Free Software Foundation; either version 2 * 12 * of the License, or (at your option) any later version. * 13 * * 14 * This program is distributed in the hope that it will be useful, * 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 17 * GNU General Public License for more details. * 18 * * 19 * You should have received a copy of the GNU General Public License * 20 * along with this program; if not, write to the Free Software * 21 * Foundation, Inc., 59 Temple Place #330, Boston, MA 02111-1307, USA. * 22 * * 23 * or visit: http://www.gnu.org/licenses/gpl.html * 24 * * 25 * * 26 * Zilog 8530 SCC Data Definitions and Structures for * 27 * Lisa serial ports * 28 \**************************************************************************************/ 29 30 31 #ifndef GOT_Z8530_REGS_H 32 #define GOT_Z8530_REGS_H 1 33 34 #define SCC_NOTHING 10 35 #define SCC_LOCALPORT 11 36 #define SCC_IMAGEWRITER 12 37 #define SCC_LOOPBACKPLUG 13 38 #define SCC_FILE 14 // same as localport??? 39 #define SCC_PIPE 15 40 #define SCC_NAMED_PIPE 16 // not yet implemented 41 #define SCC_TELNETD 17 42 #define SCC_TELNETTO 18 // not yet implemented 43 #define SCC_IMAGEWRITER_PS 19 44 #define SCC_IMAGEWRITER_PCL 20 45 46 47 48 49 #define SCC_BUFFER_SIZE 512 50 51 #define SERIAL_PORT_A_DATA 0xFCD247 52 #define SERIAL_PORT_A_CONTROL 0xFCD243 53 #define SERIAL_PORT_B_DATA 0xFCD245 54 #define SERIAL_PORT_B_CONTROL 0xFCD241 55 56 #define SCC_B_CONTROL 0 57 #define SCC_B_DATA 1 58 #define SCC_A_CONTROL 2 59 #define SCC_A_DATA 3 60 61 #define SCC_IRQ_B_EXT 1 62 #define SCC_IRQ_B_TX 2 63 #define SCC_IRQ_B_RX 4 64 65 #define SCC_IRQ_A_EXT 8 66 #define SCC_IRQ_A_TX 16 67 #define SCC_IRQ_A_RX 32 68 69 70 // These assume low bit is 1st, and will use reversebit otherwise. 71 typedef union 72 { struct { 73 #ifndef BYTES_HIGHFIRST 74 uint8 reg:3, 75 cmd:3, 76 reset:2; 77 #else 78 uint8 79 reset:2, 80 cmd:3, 81 reg:3; 82 83 #endif 84 85 } r; 86 uint8 v; 87 } wr0_t; 88 89 90 typedef union 91 { struct { 92 #ifndef BYTES_HIGHFIRST 93 uint8 94 extintenable:1, //0 95 txintenable:1, //1 96 parityspecial:1, //2 97 rxintmode:2, //34 98 waitdmareqon:1, //5 99 waitdmareqfn:1, //6 100 waitdmareqenable:1; //7 101 #else 102 uint8 103 waitdmareqenable:1, //7 104 waitdmareqfn:1, //6 105 waitdmareqon:1, //5 106 rxintmode:2, //34 107 parityspecial:1, //2 108 txintenable:1, //1 109 extintenable:1; //0 110 111 112 #endif 113 114 } r; 115 uint8 v; 116 } wr1_t; 117 118 119 typedef union 120 { struct { 121 #ifndef BYTES_HIGHFIRST 122 uint8 123 v0:1, 124 v1:1, 125 v2:1, 126 v3:1, 127 v4:1, 128 v5:1, 129 v6:1, 130 v7:1; 131 #else 132 uint8 133 v7:1, 134 v6:1, 135 v5:1, 136 v4:1, 137 v3:1, 138 v2:1, 139 v1:1, 140 v0:1; 141 142 143 #endif 144 } r; 145 uint8 v; 146 } wr2_t; 147 148 149 typedef union 150 { struct { 151 #ifndef BYTES_HIGHFIRST 152 uint8 rxenable:1, 153 syncloadinhibit:1, // 1 10 0 0 0 0 1 154 sldcaddrsearchmode:1, // 11000001 155 rxcrcenable:1, 156 enterhuntmode:1, 157 autoenables:1, 158 rxbitsperchar:2; 159 #else 160 uint8 161 rxbitsperchar:2, 162 autoenables:1, 163 enterhuntmode:1, 164 rxcrcenable:1, 165 sldcaddrsearchmode:1, // 11000001 166 syncloadinhibit:1, // 1 10 0 0 0 0 1 167 rxenable:1; 168 #endif 169 } r; 170 uint8 v; 171 } wr3_t; 172 173 typedef union 174 { struct { // 16x 175 #ifndef BYTES_HIGHFIRST 176 uint8 177 parityenable:1, //4d=01 00 11 01 == x16 clk, 2 stop bits, odd parity 178 evenparity:1, //want=00 00 01 00 =4 179 stopbits:2, 180 synchcharsize:2, 181 clockmultipliermode:2; 182 #else 183 uint8 184 clockmultipliermode:2, 185 synchcharsize:2, 186 stopbits:2, 187 evenparity:1, //want=00 00 01 00 =4 188 parityenable:1; //4d=01 00 11 01 == x16 clk, 2 stop bits, odd parity 189 #endif 190 } r; 191 uint8 v; 192 } wr4_t; 193 194 typedef union 195 { struct { 196 #ifndef BYTES_HIGHFIRST 197 uint8 198 txcrcenable:1, // 1 // 01101000 199 RTS:1, // 2 200 sldc_crc16:1, // 4 201 txenable:1, // 8 202 sendbreak:1, //16 203 txbitsperchar:2, //32+64 204 DTR:1; //128 205 #else 206 uint8 207 DTR:1, //128 208 txbitsperchar:2, //32+64 209 sendbreak:1, //16 210 txenable:1, // 8 211 sldc_crc16:1, // 4 212 RTS:1, // 2 213 txcrcenable:1; // 1 // 01101000 214 #endif 215 216 } r; 217 uint8 v; 218 } wr5_t; 219 220 221 typedef union 222 { 223 struct { 224 #ifndef BYTES_HIGHFIRST 225 uint8 226 sync0:1, 227 sync1:1, 228 sync2:1, 229 sync3:1, 230 sync4:1, 231 sync5:1, 232 sync6:1, 233 sync7:1; 234 #else 235 uint8 236 sync7:1, 237 sync6:1, 238 sync5:1, 239 sync4:1, 240 sync3:1, 241 sync2:1, 242 sync1:1, 243 sync0:1; 244 245 #endif 246 } r_monosync8; 247 248 struct { 249 #ifndef BYTES_HIGHFIRST 250 uint8 251 sync0:1, 252 sync1:1, 253 sync2:1, 254 sync3:1, 255 sync4:1, 256 sync5:1, 257 sync0a:1, 258 sync1a:1; 259 #else 260 uint8 261 sync1a:1, 262 sync0a:1, 263 sync5:1, 264 sync4:1, 265 sync3:1, 266 sync2:1, 267 sync1:1, 268 sync0:1; 269 270 #endif 271 } r_monosync6; 272 struct { 273 #ifndef BYTES_HIGHFIRST 274 uint8 275 sync0:1, 276 sync1:1, 277 sync2:1, 278 sync3:1, 279 sync4:1, 280 sync5:1, 281 sync6:1, 282 sync7:1; 283 #else 284 uint8 285 sync7:1, 286 sync6:1, 287 sync5:1, 288 sync4:1, 289 sync3:1, 290 sync2:1, 291 sync1:1, 292 sync0:1; 293 294 #endif 295 } r_bisync16; 296 struct { 297 #ifndef BYTES_HIGHFIRST 298 uint8 :4, // these are all 1 bits 299 sync1:1, 300 sync2:1, 301 sync3:1, 302 sync4:1; 303 #else 304 uint8 305 sync4:1, 306 sync3:1, 307 sync2:1, 308 sync1:1, 309 :4; // these are all 1 bits 310 #endif 311 } r_bisync12; 312 313 struct { 314 #ifndef BYTES_HIGHFIRST 315 uint8 316 adr0:1, 317 adr1:1, 318 adr2:1, 319 adr3:1, 320 adr4:1, 321 adr5:1, 322 adr6:1, 323 adr7:1; 324 #else 325 uint8 326 adr7:1, 327 adr6:1, 328 adr5:1, 329 adr4:1, 330 adr3:1, 331 adr2:1, 332 adr1:1, 333 adr0:1; 334 #endif 335 } r_sldc; 336 struct { 337 #ifndef BYTES_HIGHFIRST 338 uint8 339 :4, 340 adr4:1, 341 adr5:1, 342 adr6:1, 343 adr7:1; 344 #else 345 uint8 346 adr7:1, 347 adr6:1, 348 adr5:1, 349 adr4:1, 350 :4; 351 352 #endif 353 } r_sldc_addr_range; 354 uint8 v; 355 } wr6_t; 356 357 358 typedef union 359 { 360 struct { 361 #ifndef BYTES_HIGHFIRST 362 uint8 363 sync0:1, 364 sync1:1, 365 sync2:1, 366 sync3:1, 367 sync4:1, 368 sync5:1, 369 sync6:1, 370 sync7:1; 371 #else 372 uint8 373 sync7:1, 374 sync6:1, 375 sync5:1, 376 sync4:1, 377 sync3:1, 378 sync2:1, 379 sync1:1, 380 sync0:1; 381 382 #endif 383 } r_monosync8; 384 struct { 385 #ifndef BYTES_HIGHFIRST 386 uint8 387 :2, 388 sync0:1, 389 sync1:1, 390 sync2:1, 391 sync3:1, 392 sync4:1, 393 sync5:1; 394 #else 395 uint8 396 sync5:1, 397 sync4:1, 398 sync3:1, 399 sync2:1, 400 sync1:1, 401 sync0:1, 402 :2; 403 404 #endif 405 } r_monosync6; 406 struct { 407 #ifndef BYTES_HIGHFIRST 408 uint8 409 sync8:1, 410 sync9:1, 411 sync10:1, 412 sync11:1, 413 sync12:1, 414 sync13:1, 415 sync14:1, 416 sync15:1; 417 #else 418 uint8 419 sync15:1, 420 sync14:1, 421 sync13:1, 422 sync12:1, 423 sync11:1, 424 sync10:1, 425 sync9:1, 426 sync8:1; 427 428 #endif 429 } r_bisync16; 430 struct { 431 #ifndef BYTES_HIGHFIRST 432 uint8 433 sync4:1, 434 sync5:1, 435 sync6:1, 436 sync7:1, 437 sync8:1, 438 sync9:1, 439 sync10:1, 440 sync11:1; 441 #else 442 uint8 443 sync11:1, 444 sync10:1, 445 sync9:1, 446 sync8:1, 447 sync7:1, 448 sync6:1, 449 sync5:1, 450 sync4:1; 451 452 #endif 453 } r_bisync12; 454 // sdlc is 01111110 455 uint8 v; 456 } wr7_t; 457 458 typedef union 459 { 460 uint8 txbuffer; 461 uint8 v; 462 } wr8_t; 463 464 465 typedef union 466 { struct { 467 #ifndef BYTES_HIGHFIRST 468 uint8 469 VIS:1, // bit0 470 NV:1, // bit1 471 DLC:1, // bit2 472 MIE:1, // bit3 473 status_hi_lo:1, // controls R22B selection 474 soft_int_ack:1, 475 reset:2; 476 #else 477 uint8 478 reset:2, 479 soft_int_ack:1, 480 status_hi_lo:1, // controls R22B selection 481 MIE:1, // bit3 482 DLC:1, // bit2 483 NV:1, // bit1 484 VIS:1; // bit0 485 486 #endif 487 } r; 488 uint8 v; 489 } wr9_t; 490 491 typedef union 492 { struct { 493 #ifndef BYTES_HIGHFIRST 494 uint8 495 six_eight_bit_sync:1, 496 loopbackmode:1, 497 abort_flag_on_underrun:1, 498 sdlc_mark_flag_idle:1, 499 go_active_on_poll:1, 500 data_encoding:2, 501 crc_preset_i_o:1; 502 #else 503 uint8 504 crc_preset_i_o:1, 505 data_encoding:2, 506 go_active_on_poll:1, 507 sdlc_mark_flag_idle:1, 508 abort_flag_on_underrun:1, 509 loopbackmode:1, 510 six_eight_bit_sync:1; 511 #endif 512 } r; 513 uint8 v; 514 } wr10_t; 515 516 typedef union 517 { struct { 518 #ifndef BYTES_HIGHFIRST 519 uint8 520 xmit_extern_control:2, // $50=0 10 10 0 00 521 trxc_pin_is_output:1, 522 xmit_clock_src:2, 523 rx_clock_src:2, 524 rtxc_xtal:1; 525 #else 526 uint8 527 rtxc_xtal:1, 528 rx_clock_src:2, 529 xmit_clock_src:2, 530 trxc_pin_is_output:1, 531 xmit_extern_control:2; // $50=0 10 10 0 00 532 #endif 533 } r; 534 uint8 v; 535 } wr11_t; 536 537 typedef union 538 { struct { 539 #ifndef BYTES_HIGHFIRST 540 uint8 541 tc0:1, // low byte of time constant baud generator 542 tc1:1, 543 tc2:1, 544 tc3:1, 545 tc4:1, 546 tc5:1, 547 tc6:1, 548 tc7:1; 549 #else 550 uint8 551 tc7:1, // low byte of time constant baud generator 552 tc6:1, 553 tc5:1, 554 tc4:1, 555 tc3:1, 556 tc2:1, 557 tc1:1, 558 tc0:1; 559 #endif 560 } r; 561 uint8 v; 562 } wr12_t; 563 564 typedef union 565 { struct { // high byte of time constant baud generator 566 #ifndef BYTES_HIGHFIRST 567 uint8 tc8:1, 568 tc9:1, 569 tc10:1, 570 tc11:1, 571 tc12:1, 572 tc13:1, 573 tc14:1, 574 tc15:1; 575 #else 576 uint8 577 tc15:1, 578 tc14:1, 579 tc13:1, 580 tc12:1, 581 tc11:1, 582 tc10:1, 583 tc9:1; 584 #endif 585 } r; 586 uint8 v; 587 } wr13_t; 588 589 typedef union 590 { struct { 591 #ifndef BYTES_HIGHFIRST 592 uint8 593 br_generator_enable:1, // 1 594 br_generator_source:1, // 2 595 dtr_req_fn:1, // 4 596 auto_echo:1, // 8 597 localloopback:1, // 16 598 dpll_cmd:3; // 32- 599 #else 600 uint8 601 dpll_cmd:3, // 32- 602 localloopback:1, // 16 603 auto_echo:1, // 8 604 dtr_req_fn:1, // 4 605 br_generator_source:1, // 2 606 br_generator_enable:1; // 1 607 #endif 608 } r; 609 uint8 v; 610 } wr14_t; 611 612 typedef union 613 { struct { 614 #ifndef BYTES_HIGHFIRST 615 uint8 616 wr7prime:1, 617 zero_count_interrupt_enable:1, 618 sldc_fifo_enable:1, 619 dcd_interrupt_enable:1, 620 sync_hunt_interrupt_enable:1, 621 cts_interrupt_enable:1, 622 tx_underrun_eom_interrupt_enable:1, 623 break_abort_interrupt_enable:1; 624 #else 625 uint8 626 break_abort_interrupt_enable:1, 627 tx_underrun_eom_interrupt_enable:1, 628 cts_interrupt_enable:1, 629 sync_hunt_interrupt_enable:1, 630 dcd_interrupt_enable:1, 631 sldc_fifo_enable:1, 632 zero_count_interrupt_enable:1, 633 wr7prime:1; 634 635 636 #endif 637 } r; 638 uint8 v; 639 } wr15_t; 640 641 typedef union 642 { struct { // status bits 643 #ifndef BYTES_HIGHFIRST 644 uint8 645 rx_char_available:1, //1 //bit0 646 zero_count:1, //2 //bit1 647 tx_buffer_empty:1, //4 //bit2 648 dcd:1, //8 //bit3 649 sync_hunt:1, //16 //bit4 650 cts:1, //32 //bit5 651 tx_underrun_eom:1, //bit6 652 break_abort:1; //bit7 653 #else 654 uint8 655 break_abort:1, //bit7 656 tx_underrun_eom:1, //bit6 657 cts:1, //32 //bit5 658 sync_hunt:1, //16 //bit4 659 dcd:1, //8 //bit3 660 tx_buffer_empty:1, //4 //bit2 661 zero_count:1, //2 //bit1 662 rx_char_available:1; //1 //bit0 663 #endif 664 } r; 665 uint8 v; 666 } rr0_t; 667 668 669 typedef union 670 { struct { // special receive condition bits 671 #ifndef BYTES_HIGHFIRST 672 uint8 673 all_sent:1, 674 residue_code_2:1, 675 residue_code_1:1, 676 residue_code_0:1, 677 parity_error:1, 678 rx_overrun_error:1, 679 crc_framing_error:1, 680 sdlc_end_of_frame:1; 681 #else 682 uint8 683 sdlc_end_of_frame:1, 684 crc_framing_error:1, 685 rx_overrun_error:1, 686 parity_error:1, 687 residue_code_0:1, 688 residue_code_1:1, 689 residue_code_2:1, 690 all_sent:1; 691 #endif 692 } r; 693 uint8 v; 694 } rr1_t; 695 696 697 698 699 typedef union 700 { struct { // interrupt vector written to wr2a, wr2b is status 701 #ifndef BYTES_HIGHFIRST 702 uint8 v0:1, // Table 5-6. Interrupt Vector Modification 703 // V3|V2|V1 Status High/Status Low =0 704 v1:1, // V4|V5|V6 Status High/Status Low =1 705 v2:1, // ------------------------------------------ 706 v3:1, // 0 0 0 Ch B Transmit Buffer Empty 707 // 0 0 1 Ch B External/Status Change 708 v4:1, // 0 1 0 Ch B Receive Char. Available 709 v5:1, // 0 1 1 Ch B Special Receive Condition 710 v6:1, // 1 0 0 Ch A Transmit Buffer Empty 711 // 1 0 1 Ch A External/Status Change 712 v7:1; // 1 1 0 Ch A Receive Char. Available 713 // 1 1 1 Ch A Special Receive Condition 714 #else 715 uint8 v7:1, 716 717 v6:1, 718 v5:1, 719 v4:1, 720 721 v3:1, 722 v2:1, 723 v1:1, 724 725 v0:1; 726 #endif 727 728 } r; 729 uint8 v; 730 } rr2_t; 731 732 733 734 735 736 737 typedef union 738 { struct { 739 #ifndef BYTES_HIGHFIRST 740 uint8 741 ch_b_ext_status_irq_pending:1, // pending IRQ's 742 ch_b_tx_irq_pending:1, 743 ch_b_rx_irq_pending:1, 744 ch_a_ext_status_irq_pending:1, 745 ch_a_tx_irq_pending:1, 746 ch_a_rx_irq_pending:1, 747 :2; 748 #else 749 uint8 750 :2, 751 ch_a_rx_irq_pending:1, 752 ch_a_tx_irq_pending:1, 753 ch_a_ext_status_irq_pending:1, 754 ch_b_rx_irq_pending:1, 755 ch_b_tx_irq_pending:1, 756 ch_b_ext_status_irq_pending:1; // pending IRQ's 757 #endif 758 } r; 759 uint8 v; 760 } rr3_t; 761 762 763 typedef union 764 { 765 uint8 r; // same as rr0 on 8530, escc returns wr4 766 uint8 v; 767 } rr4_t; 768 769 typedef union 770 { 771 uint8 r; // on escc - ext read - wr5, else rr1 772 uint8 v; 773 } rr5_t; 774 775 776 777 // rr4 should return wr4 if extended read is on, otherwise rr0. 778 // rr5 should return wr5 if extended read is on, otherwise rr1 779 780 781 typedef union 782 { struct { 783 #ifndef BYTES_HIGHFIRST 784 uint8 785 bc0:1, // returns rr2 on 8530, on escc lsb of frame count on top of fifo 786 bc1:1, 787 bc2:1, 788 bc3:1, 789 bc4:1, 790 bc5:1, 791 bc6:1, 792 bc7:1; 793 #else 794 uint8 795 bc7:1, // returns rr2 on 8530, on escc lsb of frame count on top of fifo 796 bc6:1, 797 bc5:1, 798 bc4:1, 799 bc3:1, 800 bc2:1, 801 bc1:1, 802 bc0:1; 803 804 #endif 805 } r; 806 uint8 v; 807 } rr6_t; 808 809 810 typedef union 811 { struct { // on escc msb of frame count on top of fifo - 8530 image of rr3 812 #ifndef BYTES_HIGHFIRST 813 uint8 bc8:1, 814 bc9:1, 815 bc10:1, 816 bc11:1, 817 bc12:1, 818 bc13:1, 819 fifo_data_avial:1, 820 fifo_overflow_status:1; 821 #else 822 uint8 823 fifo_overflow_status:1, 824 fifo_data_avial:1, 825 bc13:1, 826 bc12:1, 827 bc11:1, 828 bc10:1, 829 bc9:1, 830 bc8:1; 831 #endif 832 } r; 833 uint8 v; 834 } rr7_t; 835 836 837 // rr8=received_Data_register 838 typedef union // received data register 839 { 840 uint8 rx_data; 841 uint8 v; 842 } rr8_t; 843 844 typedef union // on escc wr3 if extended read, else + 8530= rr13 845 { 846 uint8 r; 847 uint8 v; 848 } rr9_t; 849 850 851 // rr9 reflects wr3 if extended read option, else rr13 852 853 854 typedef union 855 { struct { 856 #ifndef BYTES_HIGHFIRST 857 uint8 858 :1, // misc status bits 859 onloop:1, // always return 0 for these in normal ops - only used in sdlc/dpll/fm modes 860 :1, 861 :1, 862 loopsending:1, 863 :1, 864 two_clocks_missing:1, 865 one_clock_missing:1; 866 #else 867 uint8 868 one_clock_missing:1, 869 two_clocks_missing:1, 870 :1, 871 loopsending:1, 872 :1, 873 :1, 874 onloop:1, // always return 0 for these in normal ops - only used in sdlc/dpll/fm modes 875 :1; // misc status bits 876 #endif 877 } r; 878 uint8 v; 879 } rr10_t; 880 881 882 typedef union 883 { 884 struct { 885 #ifndef BYTES_HIGHFIRST 886 uint8 clksel:2, // image of rr15 on 8530, on escc ext read - return wr10 887 TRxC:1, 888 xmtclksrc:2, 889 rcvclksrc:2, 890 RTxCXtal:1; 891 #else 892 uint8 893 RTxCXtal:1, 894 rcvclksrc:2, 895 xmtclksrc:2, 896 TRxC:1, 897 clksel:2; // image of rr15 on 8530, on escc ext read - return wr10 898 899 #endif 900 } r; 901 uint8 v; 902 } rr11_t; 903 904 typedef union 905 { 906 uint8 r; // returns wr12 907 uint8 v; 908 } rr12_t; 909 910 typedef union 911 { 912 uint8 r; // returns wr13 913 uint8 v; 914 } rr13_t; 915 916 typedef union 917 { 918 uint8 r; // return rr10, escc ext read - return wr7prime 919 uint8 v; 920 } rr14_t; 921 922 typedef union 923 { 924 uint8 r; // returns wr15 status IE bits 925 uint8 v; 926 } rr15_t; 927 928 929 930 // rr11 returns wr10 if extended read is on, else rr15 931 932 // rr12 returns value in wr12 933 // rr13 returns value in wr13 934 // rr14 returns wr7prime if extended read, else rr10 935 // rr15 returns wr15 936 937 #ifdef ESCC 938 typedef union 939 { struct { 940 #ifndef BYTES_HIGHFIRST 941 uint8 942 autotx:1, 943 autoeomreset:1, 944 autortsdeactivation:1, 945 rxfifohalffull:1, // on Z85C30 this is force TXD high 946 dtr_req_timing_mode:1, // on Z85C30 this is dtr_req_fastmode 947 txfifoempty:1, // on Z85c30 this is complete CRC reception 948 extendedreadenable:1, 949 :1; // reserved bit must be 0 950 #else 951 uint8 952 :1, // reserved bit must be 0 953 extendedreadenable:1, 954 txfifoempty:1, // on Z85c30 this is complete CRC reception 955 dtr_req_timing_mode:1, // on Z85C30 this is dtr_req_fastmode 956 rxfifohalffull:1, // on Z85C30 this is force TXD high 957 autortsdeactivation:1, 958 autoeomreset:1, 959 autotx:1; 960 #endif 961 } r; 962 uint8 v; 963 } rr7prime_t; 964 965 { struct { 966 #ifndef BYTES_HIGHFIRST 967 uint8 968 autotx:1, 969 autoeomreset:1, 970 autortsdeactivation:1, 971 rxfifohalffull:1, // on Z85C30 this is force TXD high 972 dtr_req_timing_mode:1, // on Z85C30 this is dtr_req_fastmode 973 txfifoempty:1, // on Z85c30 this is complete CRC reception 974 extendedreadenable:1, 975 :1; // reserved bit must be 0 976 #else 977 uint8 978 :1, // reserved bit must be 0 979 extendedreadenable:1, 980 txfifoempty:1, // on Z85c30 this is complete CRC reception 981 dtr_req_timing_mode:1, // on Z85C30 this is dtr_req_fastmode 982 rxfifohalffull:1, // on Z85C30 this is force TXD high 983 autortsdeactivation:1, 984 autoeomreset:1, 985 autotx:1; 986 987 #endif 988 } r; 989 uint8 v; 990 } wr7prime_t; 991 992 #endif 993 994 995 996 997 998 #ifdef Z85C30 999 typedef union 1000 { struct { 1001 #ifndef BYTES_HIGHFIRST 1002 uint8 1003 autotx:1, 1004 autoeomreset:1, 1005 autortsdeactivation:1, 1006 forcetxdhigh:1, 1007 dtr_req_fastmode:1, 1008 completecrcreception:1, 1009 extendedreadenable:1, 1010 :1; // reserved bit must be 0 1011 #else 1012 uint8 1013 :1, // reserved bit must be 0 1014 extendedreadenable:1, 1015 completecrcreception:1, 1016 dtr_req_fastmode:1, 1017 forcetxdhigh:1, 1018 autortsdeactivation:1, 1019 autoeomreset:1, 1020 autotx:1; 1021 1022 1023 #endif 1024 } r; 1025 uint8 v; 1026 } rr7prime_t; 1027 #endif 1028 1029 1030 typedef struct 1031 { 1032 wr0_t wr0; 1033 wr1_t wr1; 1034 wr2_t wr2; 1035 wr3_t wr3; 1036 wr4_t wr4; 1037 wr5_t wr5; 1038 wr6_t wr6; 1039 wr7_t wr7; 1040 wr8_t wr8; 1041 wr9_t wr9; 1042 wr10_t wr10; 1043 wr11_t wr11; 1044 wr12_t wr12; 1045 wr13_t wr13; 1046 wr14_t wr14; 1047 wr15_t wr15; 1048 uint8 placeholder16; 1049 1050 #ifdef ESCC 1051 wr7prime_t wr7prime; 1052 #else 1053 #ifdef Z85C30 1054 wr7prime_t wr7prime; 1055 #else 1056 uint8 placeholder; 1057 #endif 1058 #endif 1059 1060 } wr_t; 1061 1062 1063 typedef struct 1064 { 1065 rr0_t rr0; 1066 rr1_t rr1; 1067 rr2_t rr2; 1068 rr3_t rr3; 1069 rr4_t rr4; 1070 rr5_t rr5; 1071 rr6_t rr6; 1072 rr7_t rr7; 1073 rr8_t rr8; 1074 rr9_t rr9; 1075 rr10_t rr10; 1076 rr11_t rr11; 1077 rr12_t rr12; 1078 rr13_t rr13; 1079 rr14_t rr14; 1080 rr15_t rr15; 1081 1082 } rr_t; 1083 1084 1085 // SCC function hooks/(method overrides) to external device drivers 1086 typedef struct 1087 { 1088 void (*send_break)(uint8 port); 1089 void (*set_dtr)(uint8 port, uint8 value); 1090 void (*set_rts)(uint8 port, uint8 value); 1091 int (*get_dcd)(uint8 port); 1092 int (*get_cts)(uint8 port); 1093 int (*get_break)(uint8 port); 1094 void (*signal_parity_error)(uint8 port); 1095 void (*signal_crc_error)(uint8 port); 1096 void (*set_even_parity)(uint8 port); 1097 void (*set_odd_parity)(uint8 port); 1098 void (*set_no_parity)(uint8 port); 1099 void (*set_bits_per_char)(uint8 port, uint8 bitsperchar); 1100 void (*set_stop_bits)(uint8 port,uint8 stopbits); 1101 char (*read_serial_port)(int8 port); 1102 void (*write_serial_port)(int8 port, char data); 1103 void (*scc_hardware_reset_port)(int8 port); 1104 void (*scc_channel_reset_port)(int8 port); 1105 void (*set_baud_rate)(int port, uint32 baud); 1106 } sccfunc_t; 1107 1108 1109 1110 #ifdef LISAEMSCCZ8530 1111 1112 union {uint8 r[16]; // access will be scc_r[port].r[reg] or scc_r[port].s.rr0 1113 rr_t s;} scc_r[2]; 1114 1115 union {uint8 w[17]; // access will be scc_w[port].w[reg] or scc_w[port].s.wr0 1116 wr_t s;} scc_w[2]; 1117 1118 #else 1119 1120 extern union {uint8 r[16]; // access will be scc_r[port].r[reg] or scc_r[port].s.rr0 1121 rr_t s;} scc_r[2]; 1122 1123 extern union {uint8 w[17]; // access will be scc_w[port].w[reg] or scc_w[port].s.wr0 1124 wr_t s;} scc_w[2]; 1125 1126 1127 1128 1129 // prototypes 1130 extern void send_break(uint8 port); 1131 extern void set_dtr(uint8 port, uint8 value); 1132 extern void set_rts(uint8 port, uint8 value); 1133 extern int get_dcd(uint8 port); 1134 extern int get_cts(uint8 port); 1135 extern int get_break(uint8 port); 1136 extern void signal_parity_error(uint8 port); 1137 extern void signal_crc_error(uint8 port); 1138 extern void set_even_parity(uint8 port); 1139 extern void set_odd_parity(uint8 port); 1140 extern void set_no_parity(uint8 port); 1141 extern void set_bits_per_char(uint8 port, uint8 bitsperchar); 1142 extern void set_stop_bits(uint8 port,uint8 stopbits); 1143 extern char read_serial_port(int8 port); 1144 extern void write_serial_port(int8 port, char data); 1145 extern void scc_hardware_reset_port(int8 port); 1146 extern void scc_channel_reset_port(int8 port); 1147 extern void initialize_scc(void); 1148 extern void lisa_wb_Oxd200_sccz8530(uint32 address,uint8 data); 1149 extern void lisa_wb_Oxd200_sccz8530(uint32 address,uint8 data); 1150 extern void scc_control_loop(void); 1151 extern void dump_scc(void); 1152 #endif 1153 1154 1155 1156 #endif 1157