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Searched refs:SDC_GW_CTRL (Results 1 – 25 of 73) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/video/
H A Dmx3fb.c254 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
840 reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL; in lcd_enable()
841 reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in lcd_enable()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/video/
H A Dmx3fb.c159 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
752 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
753 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/video/
H A Dmx3fb.c159 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
752 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
753 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/video/
H A Dmx3fb.c159 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
752 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
753 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/video/
H A Dmx3fb.c159 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
752 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
753 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/
H A Dmx3fb.c162 #define SDC_GW_CTRL (0xB8 + IPU_BASE) macro
755 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; in ll_disp3_enable()
756 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); in ll_disp3_enable()

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