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Searched refs:SDIV_SHIFT (Results 1 – 25 of 174) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c38 #define SDIV_SHIFT 0 macro
77 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
96 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
170 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1416x_set_rate()
171 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
192 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
237 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; in clk_pll1443x_set_rate()
238 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
255 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()

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