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Searched refs:SDRAM0_CFGDATA (Results 1 – 25 of 55) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/mpl/mip405/
H A Dmip405.c364 mtdcr (SDRAM0_CFGDATA, sdram_tim); in init_sdram()
374 mtdcr (SDRAM0_CFGDATA, sdram_bank); in init_sdram()
389 mtdcr (SDRAM0_CFGDATA, tmp); in init_sdram()
399 tmp = mfdcr (SDRAM0_CFGDATA); in init_sdram()
406 mtdcr (SDRAM0_CFGDATA, tmp); in init_sdram()
410 mtdcr (SDRAM0_CFGDATA, tmp); in init_sdram()
431 tmp = mfdcr (SDRAM0_CFGDATA); in init_sdram()
433 mtdcr (SDRAM0_CFGDATA, tmp); in init_sdram()
442 mtdcr (SDRAM0_CFGDATA, tmp); in init_sdram()
635 bank_reg[0] = mfdcr (SDRAM0_CFGDATA); in initdram()
[all …]
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/mpl/pip405/
H A Dpip405.c372 mtdcr (SDRAM0_CFGDATA, tmp); in board_early_init_f()
421 mtdcr (SDRAM0_CFGDATA, bank); in board_early_init_f()
446 mtdcr (SDRAM0_CFGDATA, bank); in board_early_init_f()
469 mtdcr (SDRAM0_CFGDATA, bank); in board_early_init_f()
496 mtdcr (SDRAM0_CFGDATA, bank); in board_early_init_f()
510 mtdcr (SDRAM0_CFGDATA, tmp); in board_early_init_f()
516 mtdcr (SDRAM0_CFGDATA, tmp); in board_early_init_f()
626 bank_reg[0] = mfdcr (SDRAM0_CFGDATA); in initdram()
628 bank_reg[1] = mfdcr (SDRAM0_CFGDATA); in initdram()
630 bank_reg[2] = mfdcr (SDRAM0_CFGDATA); in initdram()
[all …]
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/csb472/
H A Dcsb472.c91 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
98 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
105 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
112 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/csb272/
H A Dcsb272.c123 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
130 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
137 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
144 tmp = mfdcr (SDRAM0_CFGDATA); in initdram()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/include/
H A Dppc4xx.h150 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
170 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
172 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/include/asm/
H A Dppc4xx.h222 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
242 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
244 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/include/asm/
H A Dppc4xx.h256 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) macro
276 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
278 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A D44x_spd_ddr.c852 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { in short_mem_test()
855 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); in short_mem_test()
1090 mtdcr(SDRAM0_CFGDATA, 0x00000000); in program_bxcr()
1236 temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | in program_bxcr()
1240 mtdcr(SDRAM0_CFGDATA, temp); in program_bxcr()

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