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Searched refs:SET_REGISTER (Results 1 – 25 of 120) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/bedbug/
H A Dregs.h172 #define SET_REGISTER( str, val ) \ macro
183 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
185 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
187 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
189 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
191 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
195 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
197 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
201 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
203 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/include/bedbug/
H A Dregs.h172 #define SET_REGISTER( str, val ) \ macro
183 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
185 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
187 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
189 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
191 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
195 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
197 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
201 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
203 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/include/bedbug/
H A Dregs.h172 #define SET_REGISTER( str, val ) \ macro
183 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
185 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
187 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
189 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
191 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
195 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
197 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
201 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
203 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/include/bedbug/
H A Dregs.h172 #define SET_REGISTER( str, val ) \ macro
183 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
185 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
187 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
189 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
191 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
195 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
197 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
201 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
203 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/include/bedbug/
H A Dregs.h172 #define SET_REGISTER( str, val ) \ macro
183 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
185 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
187 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
189 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
191 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
195 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
197 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
201 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
203 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ macro
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val )
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
198 #define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
200 #define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
[all …]

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