Home
last modified time | relevance | path

Searched refs:SHPC_SLOT_REG (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu/qemu-6.2.0/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu60/qemu-6.0.0/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
650 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu5/qemu-5.2.0/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/pci/
H A Dshpc.c57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) macro
59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
660 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); in shpc_bar_size()