Home
last modified time | relevance | path

Searched refs:SHPC_SLOT_STATE_MASK (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
329 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
342 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
363 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
328 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
341 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
362 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
328 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
341 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
362 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
329 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
342 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
363 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
262 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
285 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
325 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
338 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
359 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
329 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
342 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
363 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
329 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
342 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
363 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
328 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
341 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
362 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/pci/
H A Dshpc.c62 #define SHPC_SLOT_STATE_MASK 0x03 macro
64 ctz32(SHPC_SLOT_STATE_MASK)
214 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
220 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); in shpc_reset()
266 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
289 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
293 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); in shpc_slot_command()
329 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; in shpc_command()
342 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
363 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); in shpc_command()
[all …]