1 /* $NetBSD: siireg.h,v 1.4 1994/10/26 21:09:22 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siireg.h 8.1 (Berkeley) 6/10/93 39 * 40 * sii.h -- 41 * 42 * SII registers. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/sii.h, 53 * v 1.2 89/08/15 19:53:04 rab Exp SPRITE (DECWRL) 54 */ 55 56 #ifndef _SII 57 #define _SII 58 59 /* 60 * SII hardware registers 61 */ 62 typedef /*volatile*/ struct { 63 u_short sdb; /* SCSI Data Bus and Parity */ 64 u_short pad0; 65 u_short sc1; /* SCSI Control Signals One */ 66 u_short pad1; 67 u_short sc2; /* SCSI Control Signals Two */ 68 u_short pad2; 69 u_short csr; /* Control/Status register */ 70 u_short pad3; 71 u_short id; /* Bus ID register */ 72 u_short pad4; 73 u_short slcsr; /* Select Control and Status Register */ 74 u_short pad5; 75 u_short destat; /* Selection Detector Status Register */ 76 u_short pad6; 77 u_short dstmo; /* DSSI Timeout Register */ 78 u_short pad7; 79 u_short data; /* Data Register */ 80 u_short pad8; 81 u_short dmctrl; /* DMA Control Register */ 82 u_short pad9; 83 u_short dmlotc; /* DMA Length of Transfer Counter */ 84 u_short pad10; 85 u_short dmaddrl; /* DMA Address Register Low */ 86 u_short pad11; 87 u_short dmaddrh; /* DMA Address Register High */ 88 u_short pad12; 89 u_short dmabyte; /* DMA Initial Byte Register */ 90 u_short pad13; 91 u_short stlp; /* DSSI Short Target List Pointer */ 92 u_short pad14; 93 u_short ltlp; /* DSSI Long Target List Pointer */ 94 u_short pad15; 95 u_short ilp; /* DSSI Initiator List Pointer */ 96 u_short pad16; 97 u_short dsctrl; /* DSSI Control Register */ 98 u_short pad17; 99 u_short cstat; /* Connection Status Register */ 100 u_short pad18; 101 u_short dstat; /* Data Transfer Status Register */ 102 u_short pad19; 103 u_short comm; /* Command Register */ 104 u_short pad20; 105 u_short dictrl; /* Diagnostic Control Register */ 106 u_short pad21; 107 u_short clock; /* Diagnostic Clock Register */ 108 u_short pad22; 109 u_short bhdiag; /* Bus Handler Diagnostic Register */ 110 u_short pad23; 111 u_short sidiag; /* SCSI IO Diagnostic Register */ 112 u_short pad24; 113 u_short dmdiag; /* Data Mover Diagnostic Register */ 114 u_short pad25; 115 u_short mcdiag; /* Main Control Diagnostic Register */ 116 u_short pad26; 117 } SIIRegs; 118 119 /* 120 * SC1 - SCSI Control Signals One 121 */ 122 #define SII_SC1_MSK 0x1ff /* All possible signals on the bus */ 123 #define SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */ 124 #define SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */ 125 126 /* 127 * SC2 - SCSI Control Signals Two 128 */ 129 #define SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */ 130 131 /* 132 * CSR - Control/Status Register 133 */ 134 #define SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */ 135 #define SII_RSE 0x08 /* 1 = respond to reselections */ 136 #define SII_SLE 0x04 /* 1 = respond to selections */ 137 #define SII_PCE 0x02 /* 1 = report parity errors */ 138 #define SII_IE 0x01 /* 1 = enable interrupts */ 139 140 /* 141 * ID - Bus ID Register 142 */ 143 #define SII_ID_IO 0x8000 /* I/O */ 144 145 /* 146 * DESTAT - Selection Detector Status Register 147 */ 148 #define SII_IDMSK 0x7 /* ID of target reselected the SII */ 149 150 /* 151 * DMCTRL - DMA Control Register 152 */ 153 #define SII_ASYNC 0x00 /* REQ/ACK Offset for async mode */ 154 #define SII_SYNC 0x03 /* REQ/ACK Offset for sync mode */ 155 156 /* 157 * DMLOTC - DMA Length Of Transfer Counter 158 */ 159 #define SII_TCMSK 0x1fff /* transfer count mask */ 160 161 /* 162 * CSTAT - Connection Status Register 163 */ 164 #define SII_CI 0x8000 /* composite interrupt bit for CSTAT */ 165 #define SII_DI 0x4000 /* composite interrupt bit for DSTAT */ 166 #define SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */ 167 #define SII_BER 0x1000 /* Bus error */ 168 #define SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */ 169 #define SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */ 170 #define SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */ 171 #define SII_LDN 0x0100 /* List element Done */ 172 #define SII_SCH 0x0080 /* State Change */ 173 #define SII_CON 0x0040 /* SII is Connected to another device */ 174 #define SII_DST 0x0020 /* SII was Destination of current transfer */ 175 #define SII_TGT 0x0010 /* SII is operating as a Target */ 176 #define SII_STATE_MSK 0x0070 /* State Mask */ 177 #define SII_SWA 0x0008 /* Selected With Attention */ 178 #define SII_SIP 0x0004 /* Selection In Progress */ 179 #define SII_LST 0x0002 /* Lost arbitration */ 180 181 /* 182 * DSTAT - Data Transfer Status Register 183 */ 184 #define SII_DNE 0x2000 /* DMA transfer Done */ 185 #define SII_TCZ 0x1000 /* Transfer Count register is Zero */ 186 #define SII_TBE 0x0800 /* Transmit Buffer Empty */ 187 #define SII_IBF 0x0400 /* Input Buffer Full */ 188 #define SII_IPE 0x0200 /* Incoming Parity Error */ 189 #define SII_OBB 0x0100 /* Odd Byte Boundry */ 190 #define SII_MIS 0x0010 /* Phase Mismatch */ 191 #define SII_ATN 0x0008 /* ATN set by initiator if in Target mode */ 192 #define SII_MSG 0x0004 /* current bus state of MSG */ 193 #define SII_CD 0x0002 /* current bus state of C/D */ 194 #define SII_IO 0x0001 /* current bus state of I/O */ 195 #define SII_PHASE_MSK 0x0007 /* Phase Mask */ 196 197 /* 198 * The different phases. 199 */ 200 #define SII_MSG_IN_PHASE 0x7 201 #define SII_MSG_OUT_PHASE 0x6 202 #define SII_STATUS_PHASE 0x3 203 #define SII_CMD_PHASE 0x2 204 #define SII_DATA_IN_PHASE 0x1 205 #define SII_DATA_OUT_PHASE 0x0 206 207 /* 208 * COMM - Command Register 209 */ 210 #define SII_DMA 0x8000 /* DMA mode */ 211 #define SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */ 212 #define SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */ 213 214 /* Commands: I - Initiator, T - Target, D - Disconnected */ 215 #define SII_INXFER 0x0800 /* Information Transfer command (I,T) */ 216 #define SII_SELECT 0x0400 /* Select command (D) */ 217 #define SII_REQDATA 0x0200 /* Request Data command (T) */ 218 #define SII_DISCON 0x0100 /* Disconnect command (I,T,D) */ 219 #define SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */ 220 221 /* Command state bits same as connection status register */ 222 /* Command phase bits same as data transfer status register */ 223 224 /* 225 * DICTRL - Diagnostic Control Register 226 */ 227 #define SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */ 228 229 #define SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */ 230 /* 231 * Max DMA transfer length for SII 232 * The SII chip only has a 13 bit counter. If 8192 is used as the max count, 233 * you can't tell the difference between a count of zero and 8192. 234 * 8190 is used instead of 8191 so the count is even. 235 */ 236 #define SII_MAX_DMA_XFER_LENGTH 8192 237 238 #endif /* _SII */ 239