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Searched refs:SIMD32_SET (Results 1 – 16 of 16) sorted by relevance

/dports/devel/avr-gdb/gdb-7.3.1/sim/arm/
H A Diwmmxt.c1419 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1420 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1432 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1433 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1644 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WCMPEQ()
1645 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); in WCMPEQ()
2638 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WPACK()
3203 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
3204 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WSUB()
3216 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/arm/
H A Diwmmxt.c1418 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1419 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1431 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1432 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1643 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WCMPEQ()
1644 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); in WCMPEQ()
2640 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WPACK()
3205 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
3206 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WSUB()
3218 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Diwmmxt.c1417 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1418 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1430 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1431 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1642 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WCMPEQ()
1643 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); in WCMPEQ()
2636 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WPACK()
3201 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
3202 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WSUB()
3214 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Diwmmxt.c1417 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1418 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1430 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WADD()
1431 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1642 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WCMPEQ()
1643 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); in WCMPEQ()
2636 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); in WPACK()
3201 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
3202 SIMD32_SET (psr, overflow, SIMD_VBIT, i); in WSUB()
3214 SIMD32_SET (psr, carry, SIMD_CBIT, i); in WSUB()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Diwmmxt_helper.c34 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
159 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
160 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Diwmmxt_helper.c34 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
159 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
160 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Diwmmxt_helper.c32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
157 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
158 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Diwmmxt_helper.c34 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n))) macro
159 SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
160 SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)