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Searched refs:SLICE_WIDTH (Results 1 – 25 of 296) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/map/
H A Dcam_srl.v38 parameter SLICE_WIDTH = 4 constant
58 localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
70 wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}…
71 wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}},…
73 reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
79 reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_da…
118 reg [2**SLICE_WIDTH-1:0] srl_mem = {2**SLICE_WIDTH{1'b0}};
122 …raw_out[slice_ind][row_ind] = srl_mem[compare_data_padded[SLICE_WIDTH * slice_ind +: SLICE_WIDTH]];
168 count_next = {SLICE_WIDTH{1'b1}};
183 shift_data[i] = count_reg == write_data_padded_reg[SLICE_WIDTH * i +: SLICE_WIDTH];
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H A Dcam_bram.v38 parameter SLICE_WIDTH = 9 constant
58 localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
72 wire [SLICE_COUNT*SLICE_WIDTH-1:0] compare_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}…
73 wire [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded = {{SLICE_COUNT*SLICE_WIDTH-DATA_WIDTH{1'b0}},…
75 reg [SLICE_WIDTH-1:0] count_reg = {SLICE_WIDTH{1'b1}}, count_next;
77 reg [SLICE_COUNT*SLICE_WIDTH-1:0] ram_addr = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
83 reg [SLICE_COUNT*SLICE_WIDTH-1:0] write_data_padded_reg = {SLICE_COUNT*SLICE_WIDTH{1'b0}}, write_da…
103 erase_ram[i] = {SLICE_COUNT*SLICE_WIDTH{1'b0}};
131 localparam W = slice_ind == SLICE_COUNT-1 ? DATA_WIDTH-SLICE_WIDTH*slice_ind : SLICE_WIDTH;
151 .addrb(ram_addr[SLICE_WIDTH * slice_ind +: W]),
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H A Dcam.v40 parameter SLICE_WIDTH = 4 constant
64 .SLICE_WIDTH(SLICE_WIDTH)
84 .SLICE_WIDTH(SLICE_WIDTH)
/dports/graphics/darktable38/darktable-3.8.0/src/common/
H A Dnlmeans_core.c50 #define SLICE_WIDTH 72 macro
205 const float *const pixrow = col_sums + (SLICE_WIDTH + 2*radius)*modrow; in get_pixdiff()
216 float *const pixrow = col_sums + (SLICE_WIDTH + 2*radius)*modrow; in set_pixdiff()
224 const int stride = SLICE_WIDTH + 2*radius; in pixdiff_column_sum()
373 int sl_width = SLICE_WIDTH; in compute_slice_width()
377 if (rem < SLICE_WIDTH/2 && (width % (sl_width-4)) > rem) in compute_slice_width()
382 if (rem < SLICE_WIDTH/2 && (width % (sl_width-4)) > rem) in compute_slice_width()
411 const size_t scratch_size = (2*radius+3)*(SLICE_WIDTH + 2*radius + 1); in nlmeans_denoise()
413 …const size_t scratch_size = SLICE_WIDTH + 2*radius + 1 + 48; // getting false sharing without the … in nlmeans_denoise()
635 const size_t scratch_size = (2*radius+3)*(SLICE_WIDTH + 2*radius + 1); in nlmeans_denoise_sse2()
[all …]
/dports/graphics/darktable/darktable-3.6.1/src/common/
H A Dnlmeans_core.c50 #define SLICE_WIDTH 72 macro
205 const float *const pixrow = col_sums + (SLICE_WIDTH + 2*radius)*modrow; in get_pixdiff()
216 float *const pixrow = col_sums + (SLICE_WIDTH + 2*radius)*modrow; in set_pixdiff()
224 const int stride = SLICE_WIDTH + 2*radius; in pixdiff_column_sum()
373 int sl_width = SLICE_WIDTH; in compute_slice_width()
377 if (rem < SLICE_WIDTH/2 && (width % (sl_width-4)) > rem) in compute_slice_width()
382 if (rem < SLICE_WIDTH/2 && (width % (sl_width-4)) > rem) in compute_slice_width()
411 const size_t scratch_size = (2*radius+3)*(SLICE_WIDTH + 2*radius + 1); in nlmeans_denoise()
413 …const size_t scratch_size = SLICE_WIDTH + 2*radius + 1 + 48; // getting false sharing without the … in nlmeans_denoise()
635 const size_t scratch_size = (2*radius+3)*(SLICE_WIDTH + 2*radius + 1); in nlmeans_denoise_sse2()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ram/k3-ddrss/
H A Dlpddr4_private.h23 #define SLICE_WIDTH (0x100) macro

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