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Searched refs:SPI_DR_DR (Results 1 – 20 of 20) sorted by relevance

/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4666 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h4656 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4666 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h7036 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h7036 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */ macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h5819 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ macro
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h5819 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ macro
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h5819 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ macro
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h5819 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A Dstm32f30x.h8047 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10087 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register … macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10087 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register … macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/
H A Dstm32g431xx.h9538 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32gbk1cb.h9510 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g441xx.h9769 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g471xx.h9977 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g473xx.h10751 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g483xx.h10982 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g474xx.h14113 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro
H A Dstm32g484xx.h14344 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register … macro