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Searched refs:SPORT0_TCR2 (Results 1 – 25 of 140) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf533/
H A DBF531_def.h245 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf527/
H A DBF522_def.h115 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/
H A DADSP-EDN-BF52x-extended_def.h105 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf518/
H A DBF512_def.h121 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/
H A DADSP-EDN-extended_def.h350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
H A DADSP-EDN-DUAL-CORE-extended_def.h602 #define SPORT0_TCR2 0xFFC00804 macro
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/
H A DcdefBF532.h147 #define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)

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