/dports/emulators/qemu-utils/qemu-4.2.1/target/microblaze/ |
H A D | helper.c | 141 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 143 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 184 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 186 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 199 assert(env->sregs[SR_MSR] & MSR_IE); in mb_cpu_do_interrupt() 233 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 251 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 252 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 255 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 296 && (env->sregs[SR_MSR] & MSR_IE) in mb_cpu_exec_interrupt() [all …]
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H A D | op_helper.c | 81 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], in helper_debug() 85 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", in helper_debug() 86 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", in helper_debug() 87 (bool)(env->sregs[SR_MSR] & MSR_EIP), in helper_debug() 88 (bool)(env->sregs[SR_MSR] & MSR_IE)); in helper_debug() 136 env->sregs[SR_MSR] |= MSR_DZ; in div_prepare() 138 if ((env->sregs[SR_MSR] & MSR_EE) in div_prepare() 145 env->sregs[SR_MSR] &= ~MSR_DZ; in div_prepare() 194 && (env->sregs[SR_MSR] & MSR_EE)) { in update_fpu_flags() 439 if (!(env->sregs[SR_MSR] & MSR_EE)) { in helper_memalign() [all …]
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H A D | cpu.h | 48 #define SR_MSR 1 macro 354 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); in cpu_get_tb_cpu_state() 369 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { in cpu_mmu_index() 373 if (env->sregs[SR_MSR] & MSR_UM) { in cpu_mmu_index()
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H A D | translate.c | 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() 757 tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); in dec_bit() 1299 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rti() 1317 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rtb() 1336 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rte() [all …]
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H A D | cpu.c | 124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; in mb_cpu_reset() 126 env->sregs[SR_MSR] = 0; in mb_cpu_reset()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/microblaze/ |
H A D | helper.c | 141 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 143 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 184 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 186 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 199 assert(env->sregs[SR_MSR] & MSR_IE); in mb_cpu_do_interrupt() 233 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 251 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 252 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 255 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 296 && (env->sregs[SR_MSR] & MSR_IE) in mb_cpu_exec_interrupt() [all …]
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H A D | op_helper.c | 81 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], in helper_debug() 85 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", in helper_debug() 86 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", in helper_debug() 87 (bool)(env->sregs[SR_MSR] & MSR_EIP), in helper_debug() 88 (bool)(env->sregs[SR_MSR] & MSR_IE)); in helper_debug() 136 env->sregs[SR_MSR] |= MSR_DZ; in div_prepare() 138 if ((env->sregs[SR_MSR] & MSR_EE) in div_prepare() 145 env->sregs[SR_MSR] &= ~MSR_DZ; in div_prepare() 194 && (env->sregs[SR_MSR] & MSR_EE)) { in update_fpu_flags() 439 if (!(env->sregs[SR_MSR] & MSR_EE)) { in helper_memalign() [all …]
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H A D | cpu.h | 48 #define SR_MSR 1 macro 351 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); in cpu_get_tb_cpu_state() 366 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { in cpu_mmu_index() 370 if (env->sregs[SR_MSR] & MSR_UM) { in cpu_mmu_index()
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H A D | translate.c | 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() 757 tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); in dec_bit() 1299 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rti() 1317 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rtb() 1336 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rte() [all …]
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H A D | cpu.c | 124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; in mb_cpu_reset() 126 env->sregs[SR_MSR] = 0; in mb_cpu_reset()
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/dports/emulators/qemu42/qemu-4.2.1/target/microblaze/ |
H A D | helper.c | 141 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 143 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 184 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 186 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 199 assert(env->sregs[SR_MSR] & MSR_IE); in mb_cpu_do_interrupt() 233 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 251 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 252 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 255 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 296 && (env->sregs[SR_MSR] & MSR_IE) in mb_cpu_exec_interrupt() [all …]
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H A D | op_helper.c | 81 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], in helper_debug() 85 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", in helper_debug() 86 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", in helper_debug() 87 (bool)(env->sregs[SR_MSR] & MSR_EIP), in helper_debug() 88 (bool)(env->sregs[SR_MSR] & MSR_IE)); in helper_debug() 136 env->sregs[SR_MSR] |= MSR_DZ; in div_prepare() 138 if ((env->sregs[SR_MSR] & MSR_EE) in div_prepare() 145 env->sregs[SR_MSR] &= ~MSR_DZ; in div_prepare() 194 && (env->sregs[SR_MSR] & MSR_EE)) { in update_fpu_flags() 439 if (!(env->sregs[SR_MSR] & MSR_EE)) { in helper_memalign() [all …]
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H A D | cpu.h | 48 #define SR_MSR 1 macro 354 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); in cpu_get_tb_cpu_state() 369 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { in cpu_mmu_index() 373 if (env->sregs[SR_MSR] & MSR_UM) { in cpu_mmu_index()
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H A D | translate.c | 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() 757 tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); in dec_bit() 1299 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rti() 1317 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rtb() 1336 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rte() [all …]
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H A D | cpu.c | 124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; in mb_cpu_reset() 126 env->sregs[SR_MSR] = 0; in mb_cpu_reset()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/microblaze/ |
H A D | helper.c | 140 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 142 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 183 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 185 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 198 assert(env->sregs[SR_MSR] & MSR_IE); in mb_cpu_do_interrupt() 232 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 250 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 251 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 254 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 295 && (env->sregs[SR_MSR] & MSR_IE) in mb_cpu_exec_interrupt() [all …]
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H A D | op_helper.c | 100 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], in helper_debug() 104 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", in helper_debug() 105 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", in helper_debug() 106 (bool)(env->sregs[SR_MSR] & MSR_EIP), in helper_debug() 107 (bool)(env->sregs[SR_MSR] & MSR_IE)); in helper_debug() 155 env->sregs[SR_MSR] |= MSR_DZ; in div_prepare() 157 if ((env->sregs[SR_MSR] & MSR_EE) in div_prepare() 164 env->sregs[SR_MSR] &= ~MSR_DZ; in div_prepare() 213 && (env->sregs[SR_MSR] & MSR_EE)) { in update_fpu_flags() 458 if (!(env->sregs[SR_MSR] & MSR_EE)) { in helper_memalign() [all …]
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H A D | cpu.h | 54 #define SR_MSR 1 macro 366 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { in cpu_mmu_index() 370 if (env->sregs[SR_MSR] & MSR_UM) { in cpu_mmu_index() 387 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); in cpu_get_tb_cpu_state()
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H A D | translate.c | 154 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 167 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 439 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 451 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 452 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() 1299 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rti() 1317 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rtb() 1336 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rte() 1809 (bool)(env->sregs[SR_MSR] & MSR_EIP), in mb_cpu_dump_state() [all …]
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H A D | cpu.c | 124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; in mb_cpu_reset() 126 env->sregs[SR_MSR] = 0; in mb_cpu_reset()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/microblaze/ |
H A D | helper.c | 141 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 143 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 184 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 186 env->sregs[SR_MSR] |= MSR_EIP; in mb_cpu_do_interrupt() 199 assert(env->sregs[SR_MSR] & MSR_IE); in mb_cpu_do_interrupt() 233 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 251 env->sregs[SR_MSR] |= t; in mb_cpu_do_interrupt() 252 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 255 env->sregs[SR_MSR] |= MSR_BIP; in mb_cpu_do_interrupt() 296 && (env->sregs[SR_MSR] & MSR_IE) in mb_cpu_exec_interrupt() [all …]
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H A D | op_helper.c | 81 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], in helper_debug() 85 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", in helper_debug() 86 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", in helper_debug() 87 (bool)(env->sregs[SR_MSR] & MSR_EIP), in helper_debug() 88 (bool)(env->sregs[SR_MSR] & MSR_IE)); in helper_debug() 136 env->sregs[SR_MSR] |= MSR_DZ; in div_prepare() 138 if ((env->sregs[SR_MSR] & MSR_EE) in div_prepare() 145 env->sregs[SR_MSR] &= ~MSR_DZ; in div_prepare() 194 && (env->sregs[SR_MSR] & MSR_EE)) { in update_fpu_flags() 439 if (!(env->sregs[SR_MSR] & MSR_EE)) { in helper_memalign() [all …]
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H A D | cpu.h | 48 #define SR_MSR 1 macro 351 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); in cpu_get_tb_cpu_state() 366 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { in cpu_mmu_index() 370 if (env->sregs[SR_MSR] & MSR_UM) { in cpu_mmu_index()
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H A D | translate.c | 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() 757 tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); in dec_bit() 1299 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rti() 1317 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rtb() 1336 tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); in do_rte() [all …]
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H A D | cpu.c | 124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; in mb_cpu_reset() 126 env->sregs[SR_MSR] = 0; in mb_cpu_reset()
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