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Searched refs:SSUSB_EPCTL_CSR_BASE (Results 1 – 25 of 59) sorted by relevance

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/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h15 #define SSUSB_EPCTL_CSR_BASE 0x0800 macro
261 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
262 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
264 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
265 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h15 #define SSUSB_EPCTL_CSR_BASE 0x0800 macro
261 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
262 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
264 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
265 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h16 #define SSUSB_EPCTL_CSR_BASE 0x1800 macro
251 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
252 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
254 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
255 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)

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