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Searched refs:SSUSB_USB3_SYS_CSR_BASE (Results 1 – 25 of 59) sorted by relevance

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/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400 macro
341 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
342 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
343 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400 macro
341 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
342 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
343 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/usb/mtu3/
H A Dmtu3_hw_regs.h18 #define SSUSB_USB3_SYS_CSR_BASE 0x2400 macro
330 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
331 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
332 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)

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