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Searched refs:SX5 (Results 1 – 25 of 46) sorted by relevance

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/dports/audio/musepack/musepack_src_r475/libmpcpsy/
H A Dfft_routines.c33 #define SX5 (2./9/ 20) macro
47 …ix[3] + SX2*aix[5] + SX3*aix[7] + SX4*aix[9] + SX5*aix[11]) * (1./(SX1*SX1+SX2*SX2+SX3*SX3+SX4*SX4…
52 aix[11] -= SX5*tmp; \
63 …ix[3] + SX2*aix[5] + SX3*aix[7] + SX4*aix[9] + SX5*aix[11]) * (1./(SX1*SX1+SX2*SX2+SX3*SX3+SX4*SX4…
68 aix[11] -= SX5*tmp; \
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/VE/
H A DVECallingConv.td37 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
42 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
46 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
72 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
77 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
81 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/VE/
H A DVECallingConv.td37 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
42 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
46 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
72 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
77 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
81 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/VE/
H A DVECallingConv.td44 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
52 [SX0, SX1, SX3, SX5]>>,
92 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
97 [SX0, SX1, SX3, SX5]>>,
/dports/biology/molden/molden5.8/plush/
H A DSX51 mol="SX5" Charge="0"
/dports/science/openbabel/openbabel-3.1.1/test/pdb_ligands_sdf/
H A D3cj4_sx5.sdf111 SX5
/dports/news/nget/nget-0.27.1/test/testdata/0002/par2/
H A Dpar285 MRSP^O8<_Y+(4>[?1^_?SX5$^^>#YK]KAIX<&+O_9GB6T"!Y(/%!!4C(`4$M4
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/www/py-tuir/tuir-1.29.0/tests/cassettes/
H A Dtest_parser[livememe].yaml411 5yjv5CldZYAG0rgDpxImzTL5WkHQ/SX5+ruIxRtdmGbr0If3w+YA/bu1SJrkNA//3mycNTuaHhfC
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp69 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6,

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