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Searched refs:SZ_DEC_1M (Results 1 – 25 of 63) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c38 #define SZ_DEC_1M 1000000 macro
565 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
566 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
802 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
888 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c38 #define SZ_DEC_1M 1000000 macro
565 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
566 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
802 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
888 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c38 #define SZ_DEC_1M 1000000 macro
565 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
566 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
802 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
888 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c38 #define SZ_DEC_1M 1000000 macro
565 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
566 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
802 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
888 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c40 #define SZ_DEC_1M 1000000 macro
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M, in calc_pll_params()
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M); in calc_pll_params()
804 MAX_DDR_CLK / SZ_DEC_1M); in config_ddr_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()

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