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Searched refs:S_REG (Results 1 – 25 of 70) sorted by relevance

123

/dports/shells/ksh93/ast-93u/src/cmd/ksh93/data/
H A Dlexstates.c39 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
40 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
44 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
61 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
62 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
63 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
64 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
65 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
66 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
67 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
[all …]
/dports/shells/ksh93-devel/ast-cc1bca27/src/cmd/ksh93/data/
H A Dlexstates.c39 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
40 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
44 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
61 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
62 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
63 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
64 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
65 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
66 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
67 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
[all …]
/dports/shells/ast-ksh/ast-ksh93v/src/cmd/ksh93/data/
H A Dlexstates.c39 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
40 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
44 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
61 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
62 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
63 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
64 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
65 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
66 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
67 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG,
[all …]
/dports/shells/ksh2020/ast-ksh2020/src/cmd/ksh93/data/
H A Dlexstates.c30 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 16 - 23
31 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 24 - 31
34 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 48 - 55
46 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 128 - 135
47 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 136 - 143
48 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 144 - 151
49 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 152 - 159
50 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 160 - 167
51 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 168 - 175
52 S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, S_REG, // 176 - 183
[all …]
/dports/games/libretro-beetle_vb/beetle-vb-libretro-7412262/mednafen/hw_cpu/v810/
H A Dv810_cpu.h103 #define TESTCOND_E (S_REG[PSW]&PSW_Z)
106 #define TESTCOND_NH ( (S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY) )
110 #define TESTCOND_LT ( (!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV)) )
111 #define TESTCOND_LE ( ((!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
112 #define TESTCOND_NV (!(S_REG[PSW]&PSW_OV))
114 #define TESTCOND_NL (!(S_REG[PSW]&PSW_CY))
117 #define TESTCOND_NE (!(S_REG[PSW]&PSW_Z))
120 #define TESTCOND_H ( !((S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY)) )
124 #define TESTCOND_GE (!((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))))
125 #define TESTCOND_GT (! (((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
[all …]
H A Dv810_cpu.cpp265 if(S_REG[CHCW] & 0x2) in RDOP()
290 memset(S_REG, 0, sizeof(S_REG)); in Reset()
424 S_REG[PSW] &= ~n; in SetFlag()
427 S_REG[PSW] |= n; in SetFlag()
537 return S_REG[which]; in GetSREG()
999 S_REG[PSW] |= PSW_FRO; in CheckFPInputException()
1324 S_REG[FEPSW] = S_REG[PSW]; in Exception()
1326 S_REG[ECR] = (S_REG[ECR] & 0xFFFF) | (eCode << 16); in Exception()
1338 S_REG[EIPSW] = S_REG[PSW]; in Exception()
1339 S_REG[ECR] = (S_REG[ECR] & 0xFFFF0000) | eCode; in Exception()
[all …]
H A Dv810_oploop.inc402 S_REG[PSW] = S_REG[PSW] &~ PSW_ID;
421 S_REG[PSW] |= PSW_ID;
818 S_REG[PSW] = S_REG[FEPSW];
821 S_REG[PSW] = S_REG[EIPSW];
1006 S_REG[EIPC] = GetPC();
1007 S_REG[EIPSW] = S_REG[PSW];
1015 S_REG[PSW] |= PSW_EP;
1016 S_REG[PSW] |= PSW_ID;
1017 S_REG[PSW] &= ~PSW_AE;
1026 S_REG[PSW] &= ~PSW_IA;
[all …]
/dports/games/libretro-beetle_pcfx/beetle-pcfx-libretro-7bba669/mednafen/hw_cpu/v810/
H A Dv810_cpu.h103 #define TESTCOND_E (S_REG[PSW]&PSW_Z)
106 #define TESTCOND_NH ( (S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY) )
110 #define TESTCOND_LT ( (!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV)) )
111 #define TESTCOND_LE ( ((!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
112 #define TESTCOND_NV (!(S_REG[PSW]&PSW_OV))
114 #define TESTCOND_NL (!(S_REG[PSW]&PSW_CY))
117 #define TESTCOND_NE (!(S_REG[PSW]&PSW_Z))
120 #define TESTCOND_H ( !((S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY)) )
124 #define TESTCOND_GE (!((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))))
125 #define TESTCOND_GT (! (((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
[all …]
H A Dv810_cpu.cpp281 if(S_REG[CHCW] & 0x2) in RDOP()
306 memset(S_REG, 0, sizeof(S_REG)); in Reset()
450 S_REG[PSW] &= ~n; in SetFlag()
453 S_REG[PSW] |= n; in SetFlag()
577 ret = S_REG[which]; in GetSREG()
1164 S_REG[PSW] |= PSW_FRO; in FPU_DoException()
1411 S_REG[FEPSW] = S_REG[PSW]; in Exception()
1413 S_REG[ECR] = (S_REG[ECR] & 0xFFFF) | (eCode << 16); in Exception()
1425 S_REG[EIPSW] = S_REG[PSW]; in Exception()
1426 S_REG[ECR] = (S_REG[ECR] & 0xFFFF0000) | eCode; in Exception()
[all …]
H A Dv810_oploop.inc404 S_REG[PSW] = S_REG[PSW] &~ PSW_ID;
423 S_REG[PSW] |= PSW_ID;
830 S_REG[PSW] = S_REG[FEPSW];
833 S_REG[PSW] = S_REG[EIPSW];
1021 S_REG[EIPC] = GetPC();
1022 S_REG[EIPSW] = S_REG[PSW];
1030 S_REG[PSW] |= PSW_EP;
1031 S_REG[PSW] |= PSW_ID;
1032 S_REG[PSW] &= ~PSW_AE;
1041 S_REG[PSW] &= ~PSW_IA;
[all …]
/dports/emulators/mednafen/mednafen/src/hw_cpu/v810/
H A Dv810_cpu.h104 #define TESTCOND_E (S_REG[PSW]&PSW_Z)
107 #define TESTCOND_NH ( (S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY) )
111 #define TESTCOND_LT ( (!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV)) )
112 #define TESTCOND_LE ( ((!!(S_REG[PSW]&PSW_S)) ^ (!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
113 #define TESTCOND_NV (!(S_REG[PSW]&PSW_OV))
115 #define TESTCOND_NL (!(S_REG[PSW]&PSW_CY))
118 #define TESTCOND_NE (!(S_REG[PSW]&PSW_Z))
121 #define TESTCOND_H ( !((S_REG[PSW]&PSW_Z) || (S_REG[PSW]&PSW_CY)) )
125 #define TESTCOND_GE (!((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))))
126 #define TESTCOND_GT (! (((!!(S_REG[PSW]&PSW_S))^(!!(S_REG[PSW]&PSW_OV))) || (S_REG[PSW]…
[all …]
H A Dv810_cpu.cpp283 if(S_REG[CHCW] & 0x2) in RDOP()
308 memset(S_REG, 0, sizeof(S_REG)); in Reset()
443 S_REG[PSW] &= ~n; in SetFlag()
446 S_REG[PSW] |= n; in SetFlag()
570 ret = S_REG[which]; in GetSREG()
1174 S_REG[PSW] |= PSW_FRO; in FPU_DoException()
1422 S_REG[FEPSW] = S_REG[PSW]; in Exception()
1424 S_REG[ECR] = (S_REG[ECR] & 0xFFFF) | (eCode << 16); in Exception()
1436 S_REG[EIPSW] = S_REG[PSW]; in Exception()
1437 S_REG[ECR] = (S_REG[ECR] & 0xFFFF0000) | eCode; in Exception()
[all …]
H A Dv810_oploop.inc442 S_REG[PSW] = S_REG[PSW] &~ PSW_ID;
461 S_REG[PSW] |= PSW_ID;
868 S_REG[PSW] = S_REG[FEPSW];
871 S_REG[PSW] = S_REG[EIPSW];
1059 S_REG[EIPC] = GetPC();
1060 S_REG[EIPSW] = S_REG[PSW];
1068 S_REG[PSW] |= PSW_EP;
1069 S_REG[PSW] |= PSW_ID;
1070 S_REG[PSW] &= ~PSW_AE;
1079 S_REG[PSW] &= ~PSW_IA;
[all …]
/dports/lang/sdcc/sdcc-4.0.0/sdas/as8051/
H A Di51pst.c148 { NULL, "r0", S_REG, 0, R0 },
149 { NULL, "r1", S_REG, 0, R1 },
150 { NULL, "r2", S_REG, 0, R2 },
151 { NULL, "r3", S_REG, 0, R3 },
152 { NULL, "r4", S_REG, 0, R4 },
153 { NULL, "r5", S_REG, 0, R5 },
154 { NULL, "r6", S_REG, 0, R6 },
155 { NULL, "r7", S_REG, 0, R7 },
H A Di51mch.c140 case S_REG: in machine()
181 case S_REG: in machine()
236 case S_REG: in machine()
291 case S_REG: in machine()
324 case S_REG: in machine()
333 case S_REG: in machine()
381 case S_REG: in machine()
512 case S_REG: in machine()
552 case S_REG: in machine()
H A Di51adr.c141 esp->e_mode = S_REG; in addr()
240 case S_REG: in reg()
H A Di8051.h86 #define S_REG 35 /* Register R0-R7 */ macro
/dports/lang/sdcc/sdcc-4.0.0/sdas/as8xcxxx/
H A Dds8pst.c240 { NULL, "r0", S_REG, 0, R0 },
241 { NULL, "r1", S_REG, 0, R1 },
242 { NULL, "r2", S_REG, 0, R2 },
243 { NULL, "r3", S_REG, 0, R3 },
244 { NULL, "r4", S_REG, 0, R4 },
245 { NULL, "r5", S_REG, 0, R5 },
246 { NULL, "r6", S_REG, 0, R6 },
247 { NULL, "r7", S_REG, 0, R7 },
H A Dds8mch.c270 case S_REG: in machine()
311 case S_REG: in machine()
366 case S_REG: in machine()
421 case S_REG: in machine()
454 case S_REG: in machine()
463 case S_REG: in machine()
511 case S_REG: in machine()
645 case S_REG: in machine()
685 case S_REG: in machine()
H A Dds8adr.c144 esp->e_mode = S_REG; in addr()
243 case S_REG: in reg()
H A Dds8.h63 #define S_REG 35 /* Register R0-R7 */ macro
/dports/lang/sdcc/sdcc-4.0.0/sdas/asstm8/
H A Dstm8mch.c199 if ((t2 == S_REG) && (v2 == SP) &&
212 if ((t2 != S_REG) || (v2 != A)) {
985 if ((t1 == S_REG) && (t2 == S_REG)) {
1419 if (t1 == S_REG) {
1433 if(t1 != S_REG) {
1455 case S_REG:
1479 if (t1 == S_REG) {
1510 if ((t1 == S_REG) && (t2 == S_REG)) {
1524 case S_REG:
1542 case S_REG:
[all …]
H A Dstm8.h67 #define S_REG 0x00 macro
/dports/net/freeswitch/freeswitch-1.10.3.-release/libs/freetdm/src/ftmod/ftmod_sangoma_ss7/
H A Dftmod_sangoma_ss7_m2ua.c185 cntrl.hdr.response.mem.region = S_REG; in ftmod_ss7_tucl_shutdown()
214 cntrl.hdr.response.mem.region = S_REG; in ftmod_ss7_m2ua_shutdown()
243 cntrl.hdr.response.mem.region = S_REG; in ftmod_ss7_sctp_shutdown()
439 pCfg->uiMemId.region = S_REG; in ftmod_tucl_sap_config()
583 c->memId.region = S_REG; in ftmod_sctp_tsap_config()
634 c->memId.region = S_REG; in ftmod_sctp_sap_config()
712 cfg.hdr.response.mem.region = S_REG; in ftmod_m2ua_gen_config()
852 cfg.hdr.response.mem.region = S_REG; in ftmod_m2ua_sctsap_config()
1672 ssta.hdr.response.mem.region = S_REG; in ftmod_sctp_ssta_req()
1711 ssta.hdr.response.mem.region = S_REG; in ftmod_m2ua_ssta_req()
[all …]
/dports/shells/ksh2020/ast-ksh2020/src/cmd/ksh93/include/
H A Dlexstates.h33 #define S_REG 6 // non-special characters macro

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