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Searched refs:SecondAND (Results 1 – 3 of 3) sorted by relevance

/dports/devel/taskflow/taskflow-3.2.0/3rd-party/tbb/examples/graph/logic_sim/
H A Done_bit_adder.h54 and_gate<2> SecondAND; variable
61 SecondXOR(g), FirstAND(g), SecondAND(g), FirstOR(g) { in one_bit_adder()
68 FirstAND(src.my_graph), SecondAND(src.my_graph), FirstOR(src.my_graph) in one_bit_adder()
84 make_edge(CI_port, input_port<1>(SecondAND)); in make_connections()
86 make_edge(FirstXOR, input_port<0>(SecondAND)); in make_connections()
87 make_edge(SecondAND, input_port<0>(FirstOR)); in make_connections()
95 …pe::add_visible_nodes(A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR ); in set_up_composite()
/dports/devel/tbb/oneTBB-2020.3/examples/graph/logic_sim/
H A Done_bit_adder.h54 and_gate<2> SecondAND; variable
61 SecondXOR(g), FirstAND(g), SecondAND(g), FirstOR(g) { in one_bit_adder()
68 FirstAND(src.my_graph), SecondAND(src.my_graph), FirstOR(src.my_graph) in one_bit_adder()
84 make_edge(CI_port, input_port<1>(SecondAND)); in make_connections()
86 make_edge(FirstXOR, input_port<0>(SecondAND)); in make_connections()
87 make_edge(SecondAND, input_port<0>(FirstOR)); in make_connections()
95 …pe::add_visible_nodes(A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR ); in set_up_composite()
/dports/devel/onetbb/oneTBB-2021.4.0/examples/graph/logic_sim/
H A Done_bit_adder.hpp56 and_gate<2> SecondAND; member in one_bit_adder
73 SecondAND(g), in one_bit_adder()
87 SecondAND(src.my_graph), in one_bit_adder()
102 make_edge(CI_port, input_port<1>(SecondAND)); in make_connections()
104 make_edge(FirstXOR, input_port<0>(SecondAND)); in make_connections()
105 make_edge(SecondAND, input_port<0>(FirstOR)); in make_connections()
115 A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR); in set_up_composite()