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Searched refs:Set_PSL_Clock_Sensitivity (Results 1 – 5 of 5) sorted by relevance

/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/
H A Dnodes.py2834 Set_PSL_Clock_Sensitivity = libghdl.vhdl__nodes__set_psl_clock_sensitivity variable
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/
H A Dvhdl-canon.adb1726 Set_PSL_Clock_Sensitivity (Stmt, List);
H A Dvhdl-nodes.ads9219 procedure Set_PSL_Clock_Sensitivity (N : Iir; List : Iir_List); subprogspec
H A Dvhdl-nodes.adb7285 procedure Set_PSL_Clock_Sensitivity (N : Iir; List : Iir_List) is subprogram
7291 end Set_PSL_Clock_Sensitivity;
H A Dvhdl-nodes_meta.adb7181 Set_PSL_Clock_Sensitivity (N, V);