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Searched refs:StageInst1 (Results 1 – 17 of 17) sorted by relevance

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2562 int StageInst1 = stageScheduled(SU); in orderDependence() local
2581 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2585 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2598 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2606 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2611 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2624 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2632 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2641 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2560 int StageInst1 = stageScheduled(SU); in orderDependence() local
2579 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2583 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2587 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2596 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2604 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2609 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2622 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2630 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2639 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp2468 int StageInst1 = stageScheduled(SU); in orderDependence() local
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2491 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2495 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2504 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2512 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2530 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2538 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2547 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2545 int StageInst1 = stageScheduled(SU); in orderDependence() local
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2607 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2615 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2624 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp2545 int StageInst1 = stageScheduled(SU); in orderDependence() local
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2607 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2615 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2624 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2569 int StageInst1 = stageScheduled(SU); in orderDependence() local
2588 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2592 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2596 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2605 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2613 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2618 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2631 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2639 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2648 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp2560 int StageInst1 = stageScheduled(SU); in orderDependence() local
2579 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2583 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2587 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2596 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2604 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2609 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2622 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2630 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2639 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2468 int StageInst1 = stageScheduled(SU); in orderDependence() local
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2491 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2495 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2504 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2512 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2530 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2538 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2547 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2545 int StageInst1 = stageScheduled(SU); in orderDependence() local
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2607 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2615 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2624 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2544 int StageInst1 = stageScheduled(SU); in orderDependence() local
2563 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2567 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2571 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2580 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2588 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2593 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2606 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2614 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2623 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2545 int StageInst1 = stageScheduled(SU); in orderDependence() local
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2607 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2615 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2624 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2569 int StageInst1 = stageScheduled(SU); in orderDependence() local
2588 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2592 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2596 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2605 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2613 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2618 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2631 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2639 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2648 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2468 int StageInst1 = stageScheduled(SU); in orderDependence() local
2487 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
2491 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
2495 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2504 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2512 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2530 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
2538 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
2547 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp2545 int StageInst1 = stageScheduled(SU);
2564 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2568 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
2572 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
2581 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
2589 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
2594 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
2607 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
2615 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) {
2624 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {
/dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp3495 int StageInst1 = stageScheduled(SU); in orderDependence() local
3514 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
3518 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
3522 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
3531 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
3539 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
3544 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
3557 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
3565 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { in orderDependence()
3574 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp3296 int StageInst1 = stageScheduled(SU); in orderDependence() local
3315 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
3319 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
3323 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
3332 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
3340 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
3345 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
3358 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
3367 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
/dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/
H A DMachinePipeliner.cpp3779 int StageInst1 = stageScheduled(SU); in orderDependence() local
3798 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
3802 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
3806 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
3815 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
3823 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
3828 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
3841 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()
3850 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { in orderDependence()