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Searched refs:Sub1_Mi (Results 1 – 25 of 28) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2682 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUDIV_UREM64Impl() local
2704 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1860 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1878 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2682 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUDIV_UREM64Impl() local
2704 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1860 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1878 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2920 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUDIV_UREM64Impl() local
2942 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1874 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1892 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3012 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3034 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1934 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1952 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3012 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3034 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1934 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1952 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2915 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUDIV_UREM64Impl() local
2937 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
H A DAMDGPUISelLowering.cpp1877 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1895 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3012 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3034 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1934 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1952 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3081 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3103 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1927 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1945 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3012 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3034 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPUISelLowering.cpp1934 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1952 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2915 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUDIV_UREM64Impl() local
2937 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3012 auto Sub1_Mi = B.buildSub(S32, NumerHi, Mul3_Hi); in legalizeUnsignedDIV_REM64Impl() local
3034 auto Sub2_Mi = B.buildUSube(S32, S1, Sub1_Mi, DenomHi, Sub1_Lo.getReg(1)); in legalizeUnsignedDIV_REM64Impl()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1659 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1677 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1745 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1763 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1745 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1763 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1745 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1763 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1679 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi); in LowerUDIVREM64() local
1697 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi, in LowerUDIVREM64()

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