/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1629 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1631 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1640 .addImm(SubHi); in processBlock() 1694 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1696 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1704 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1962 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1963 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1965 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1623 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1625 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1634 .addImm(SubHi); in processBlock() 1688 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1690 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1629 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1631 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1640 .addImm(SubHi); in processBlock() 1694 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1696 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1704 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1962 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1963 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1965 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1623 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1625 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1634 .addImm(SubHi); in processBlock() 1688 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1690 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1956 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1957 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1959 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1962 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1964 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1962 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1964 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1962 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1964 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1629 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1631 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1640 .addImm(SubHi); in processBlock() 1694 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1696 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1704 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1962 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1963 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1965 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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H A D | HexagonConstPropagation.cpp | 1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate() local 1962 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate() 1964 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1623 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1625 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1634 .addImm(SubHi); in processBlock() 1688 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1690 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1635 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1644 .addImm(SubHi); in processBlock() 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 445 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 450 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1625 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1627 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1636 .addImm(SubHi); in processBlock() 1690 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1692 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1700 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 444 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 445 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 446 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 451 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1626 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1628 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1637 .addImm(SubHi); in processBlock() 1691 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1693 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1701 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 444 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() local 445 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence() 446 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence() 451 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence() 1626 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); in processBlock() local 1628 BitTracker::RegisterRef TH = { R, SubHi }; in processBlock() 1637 .addImm(SubHi); in processBlock() 1691 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local 1693 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy() 1701 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); in propagateRegCopy() local [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 443 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); 444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); 445 if (Sub1 == SubLo && Sub2 == SubHi) { 450 if (Sub1 == SubHi && Sub2 == SubLo) { 1633 unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi); 1635 BitTracker::RegisterRef TH = { R, SubHi }; 1644 .addImm(SubHi); 1698 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); 1708 unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi); [all …]
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