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Searched refs:TCG_PHYS_ADDR_BITS (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu60/qemu-6.0.0/target/i386/tcg/
H A Dhelper-tcg.h29 # define TCG_PHYS_ADDR_BITS 40 macro
31 # define TCG_PHYS_ADDR_BITS 36 macro
34 QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/i386/tcg/
H A Dhelper-tcg.h29 # define TCG_PHYS_ADDR_BITS 40 macro
31 # define TCG_PHYS_ADDR_BITS 36 macro
34 QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
/dports/emulators/qemu/qemu-6.2.0/target/i386/tcg/
H A Dhelper-tcg.h29 # define TCG_PHYS_ADDR_BITS 40 macro
31 # define TCG_PHYS_ADDR_BITS 36 macro
34 QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/i386/
H A Dcpu.h1691 # define TCG_PHYS_ADDR_BITS 40 macro
1693 # define TCG_PHYS_ADDR_BITS 36 macro
1696 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c5010 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
5012 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
5021 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu-utils/qemu-4.2.1/target/i386/
H A Dcpu.h1931 # define TCG_PHYS_ADDR_BITS 40 macro
1933 # define TCG_PHYS_ADDR_BITS 36 macro
1936 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c6399 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
6401 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
6410 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu5/qemu-5.2.0/target/i386/
H A Dcpu.h1964 # define TCG_PHYS_ADDR_BITS 40 macro
1966 # define TCG_PHYS_ADDR_BITS 36 macro
1969 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c6626 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
6628 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
6637 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/i386/
H A Dcpu.h1945 # define TCG_PHYS_ADDR_BITS 40 macro
1947 # define TCG_PHYS_ADDR_BITS 36 macro
1950 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c6586 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
6588 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
6597 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu42/qemu-4.2.1/target/i386/
H A Dcpu.h1931 # define TCG_PHYS_ADDR_BITS 40 macro
1933 # define TCG_PHYS_ADDR_BITS 36 macro
1936 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c6399 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
6401 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
6410 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/i386/
H A Dcpu.h1943 # define TCG_PHYS_ADDR_BITS 40 macro
1945 # define TCG_PHYS_ADDR_BITS 36 macro
1948 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
H A Dcpu.c6640 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { in x86_cpu_realizefn()
6642 TCG_PHYS_ADDR_BITS); in x86_cpu_realizefn()
6651 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/i386/
H A Dcpu.c6221 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
/dports/emulators/qemu/qemu-6.2.0/target/i386/
H A Dcpu.c6387 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
/dports/emulators/qemu60/qemu-6.0.0/target/i386/
H A Dcpu.c6814 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()