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Searched refs:TCG_REG_TB (Results 1 – 25 of 27) sorted by relevance

12

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/sparc/
H A Dtcg-target.inc.c90 #define TCG_REG_TB TCG_REG_I1 macro
322 insn ^= INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2); in patch_reloc()
576 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); in tcg_out_ld_ptr()
1068 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); in tcg_target_qemu_prologue()
1069 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_qemu_prologue()
1378 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); in tcg_out_op()
1386 tcg_out_ld_ptr(s, TCG_REG_TB, in tcg_out_op()
1388 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); in tcg_out_op()
1398 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); in tcg_out_op()
1401 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, in tcg_out_op()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/sparc/
H A Dtcg-target.inc.c90 #define TCG_REG_TB TCG_REG_I1 macro
450 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); in tcg_out_movi_int()
549 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); in tcg_out_ld_ptr()
1037 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); in tcg_target_qemu_prologue()
1038 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_qemu_prologue()
1345 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); in tcg_out_op()
1353 tcg_out_ld_ptr(s, TCG_REG_TB, in tcg_out_op()
1355 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); in tcg_out_op()
1365 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); in tcg_out_op()
1368 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, in tcg_out_op()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/sparc/
H A Dtcg-target.inc.c90 #define TCG_REG_TB TCG_REG_I1 macro
450 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); in tcg_out_movi_int()
549 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); in tcg_out_ld_ptr()
1037 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); in tcg_target_qemu_prologue()
1038 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_qemu_prologue()
1345 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); in tcg_out_op()
1353 tcg_out_ld_ptr(s, TCG_REG_TB, in tcg_out_op()
1355 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); in tcg_out_op()
1365 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); in tcg_out_op()
1368 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, in tcg_out_op()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/tcg/sparc/
H A Dtcg-target.inc.c90 #define TCG_REG_TB TCG_REG_I1 macro
450 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); in tcg_out_movi_int()
549 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); in tcg_out_ld_ptr()
1037 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); in tcg_target_qemu_prologue()
1038 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_qemu_prologue()
1345 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); in tcg_out_op()
1353 tcg_out_ld_ptr(s, TCG_REG_TB, in tcg_out_op()
1355 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); in tcg_out_op()
1365 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); in tcg_out_op()
1368 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, in tcg_out_op()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/sparc/
H A Dtcg-target.inc.c90 #define TCG_REG_TB TCG_REG_I1 macro
450 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); in tcg_out_movi_int()
549 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); in tcg_out_ld_ptr()
1037 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); in tcg_target_qemu_prologue()
1038 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_qemu_prologue()
1345 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); in tcg_out_op()
1353 tcg_out_ld_ptr(s, TCG_REG_TB, in tcg_out_op()
1355 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); in tcg_out_op()
1365 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); in tcg_out_op()
1368 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, in tcg_out_op()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/ppc/
H A Dtcg-target.inc.c45 #define TCG_REG_TB TCG_REG_R31 macro
651 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); in tcg_out_movi_int()
703 tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); in tcg_out_movi_int()
1373 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); in tb_target_set_jmp_target()
1379 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); in tb_target_set_jmp_target()
1380 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); in tb_target_set_jmp_target()
2012 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2013 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2023 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, in tcg_out_op()
2026 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); in tcg_out_op()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/sparc/
H A Dtcg-target.c.inc110 #define TCG_REG_TB TCG_REG_I1
536 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
1021 /* We choose TCG_REG_TB such that no move is required. */
1023 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
1024 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
1331 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
1346 TCG_REG_TB to the beginning of this TB. */
1350 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
1353 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
1361 tcg_out_mov_delay(s, TCG_REG_TB, a0);
[all …]
/dports/emulators/qemu/qemu-6.2.0/tcg/sparc/
H A Dtcg-target.c.inc110 #define TCG_REG_TB TCG_REG_I1
536 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
1021 /* We choose TCG_REG_TB such that no move is required. */
1023 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
1024 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
1331 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
1346 TCG_REG_TB to the beginning of this TB. */
1350 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
1353 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
1361 tcg_out_mov_delay(s, TCG_REG_TB, a0);
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tcg/sparc/
H A Dtcg-target.c.inc110 #define TCG_REG_TB TCG_REG_I1
427 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD);
526 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
1012 /* We choose TCG_REG_TB such that no move is required. */
1014 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
1015 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
1322 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
1337 TCG_REG_TB to the beginning of this TB. */
1341 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
1344 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/tcg/sparc/
H A Dtcg-target.c.inc90 #define TCG_REG_TB TCG_REG_I1
544 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
1030 /* We choose TCG_REG_TB such that no move is required. */
1032 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
1033 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
1340 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
1348 tcg_out_ld_ptr(s, TCG_REG_TB,
1356 TCG_REG_TB to the beginning of this TB. */
1360 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
1363 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/s390/
H A Dtcg-target.inc.c55 #define TCG_REG_TB TCG_REG_R12 macro
660 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); in tcg_out_movi_int()
755 tcg_out_ld(s, type, dest, TCG_REG_TB, disp); in tcg_out_ld_abs()
1020 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_ori()
1055 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_xori()
1785 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, in tcg_out_op()
1788 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); in tcg_out_op()
1797 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); in tcg_out_op()
1804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); in tcg_out_op()
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_init()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/s390/
H A Dtcg-target.inc.c55 #define TCG_REG_TB TCG_REG_R12 macro
660 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); in tcg_out_movi_int()
755 tcg_out_ld(s, type, dest, TCG_REG_TB, disp); in tcg_out_ld_abs()
1020 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_ori()
1055 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_xori()
1785 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, in tcg_out_op()
1788 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); in tcg_out_op()
1797 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); in tcg_out_op()
1804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); in tcg_out_op()
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_init()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/tcg/s390/
H A Dtcg-target.inc.c55 #define TCG_REG_TB TCG_REG_R12 macro
660 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); in tcg_out_movi_int()
755 tcg_out_ld(s, type, dest, TCG_REG_TB, disp); in tcg_out_ld_abs()
1020 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_ori()
1055 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_xori()
1785 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, in tcg_out_op()
1788 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); in tcg_out_op()
1797 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); in tcg_out_op()
1804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); in tcg_out_op()
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_init()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/s390/
H A Dtcg-target.inc.c55 #define TCG_REG_TB TCG_REG_R12 macro
652 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); in tcg_out_movi_int()
747 tcg_out_ld(s, type, dest, TCG_REG_TB, disp); in tcg_out_ld_abs()
1012 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_ori()
1047 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_xori()
1781 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, in tcg_out_op()
1784 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); in tcg_out_op()
1793 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); in tcg_out_op()
1800 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); in tcg_out_op()
2524 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_init()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/s390/
H A Dtcg-target.inc.c55 #define TCG_REG_TB TCG_REG_R12 macro
660 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); in tcg_out_movi_int()
755 tcg_out_ld(s, type, dest, TCG_REG_TB, disp); in tcg_out_ld_abs()
1020 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_ori()
1055 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); in tgen_xori()
1785 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, in tcg_out_op()
1788 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); in tcg_out_op()
1797 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); in tcg_out_op()
1804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); in tcg_out_op()
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); in tcg_target_init()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/ppc/
H A Dtcg-target.inc.c48 #define TCG_REG_TB TCG_REG_R31 macro
898 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); in tcg_out_movi_int()
972 load_insn |= RA(TCG_REG_TB); in tcg_out_dupi_vec()
1742 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); in tb_target_set_jmp_target()
1748 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); in tb_target_set_jmp_target()
1749 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); in tb_target_set_jmp_target()
2380 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2381 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2391 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, in tcg_out_op()
2394 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); in tcg_out_op()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/ppc/
H A Dtcg-target.inc.c48 #define TCG_REG_TB TCG_REG_R31 macro
898 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); in tcg_out_movi_int()
972 load_insn |= RA(TCG_REG_TB); in tcg_out_dupi_vec()
1742 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); in tb_target_set_jmp_target()
1748 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); in tb_target_set_jmp_target()
1749 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); in tb_target_set_jmp_target()
2380 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2381 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2391 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, in tcg_out_op()
2394 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); in tcg_out_op()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/tcg/ppc/
H A Dtcg-target.inc.c48 #define TCG_REG_TB TCG_REG_R31 macro
898 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); in tcg_out_movi_int()
972 load_insn |= RA(TCG_REG_TB); in tcg_out_dupi_vec()
1742 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); in tb_target_set_jmp_target()
1748 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); in tb_target_set_jmp_target()
1749 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); in tb_target_set_jmp_target()
2380 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2381 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2391 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, in tcg_out_op()
2394 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); in tcg_out_op()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/ppc/
H A Dtcg-target.inc.c48 #define TCG_REG_TB TCG_REG_R31 macro
898 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); in tcg_out_movi_int()
972 load_insn |= RA(TCG_REG_TB); in tcg_out_dupi_vec()
1742 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); in tb_target_set_jmp_target()
1748 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); in tb_target_set_jmp_target()
1749 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); in tb_target_set_jmp_target()
2380 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2381 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); in tcg_out_op()
2391 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, in tcg_out_op()
2394 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); in tcg_out_op()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/tcg/ppc/
H A Dtcg-target.c.inc48 #define TCG_REG_TB TCG_REG_R31
894 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
968 load_insn |= RA(TCG_REG_TB);
1738 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1744 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1745 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
2376 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2377 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2387 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2390 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/ppc/
H A Dtcg-target.c.inc63 #define TCG_REG_TB TCG_REG_R31
1008 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
1093 load_insn |= RA(TCG_REG_TB);
1857 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1863 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1864 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
2495 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2496 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2506 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2509 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
[all …]
/dports/emulators/qemu/qemu-6.2.0/tcg/ppc/
H A Dtcg-target.c.inc63 #define TCG_REG_TB TCG_REG_R31
1008 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
1093 load_insn |= RA(TCG_REG_TB);
1857 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1863 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1864 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
2495 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2496 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2506 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2509 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tcg/ppc/
H A Dtcg-target.c.inc48 #define TCG_REG_TB TCG_REG_R31
855 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
940 load_insn |= RA(TCG_REG_TB);
1704 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1710 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1711 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
2343 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2344 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2354 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2357 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/s390/
H A Dtcg-target.c.inc68 #define TCG_REG_TB TCG_REG_R12
627 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
723 tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
1739 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
1742 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
1747 TCG_REG_TB to the beginning of this TB. */
1752 tcg_out_insn(s, RXY, LAY, TCG_REG_TB,
1753 TCG_REG_TB, TCG_REG_NONE, ofs);
1760 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
2485 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tcg/s390/
H A Dtcg-target.c.inc68 #define TCG_REG_TB TCG_REG_R12
630 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
726 tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
1742 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
1745 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
1750 TCG_REG_TB to the beginning of this TB. */
1755 tcg_out_insn(s, RXY, LAY, TCG_REG_TB,
1756 TCG_REG_TB, TCG_REG_NONE, ofs);
1763 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
2466 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
[all …]

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