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Searched refs:TCG_TARGET_NB_REGS (Results 1 – 25 of 245) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/tcg/tci/
H A Dtcg-target.h138 #define TCG_TARGET_NB_REGS 16 macro
151 #if TCG_TARGET_NB_REGS >= 16
160 #if TCG_TARGET_NB_REGS >= 32
183 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
186 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
H A Dtcg-target.inc.c283 #if TCG_TARGET_NB_REGS >= 16
312 #if TCG_TARGET_NB_REGS >= 16
332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
341 #if TCG_TARGET_NB_REGS >= 16
350 #if TCG_TARGET_NB_REGS >= 32
396 ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; in target_parse_constraint()
434 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); in tcg_out_r()
877 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
879 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
881 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
/dports/emulators/qemu5/qemu-5.2.0/tcg/tci/
H A Dtcg-target.h138 #define TCG_TARGET_NB_REGS 16 macro
151 #if TCG_TARGET_NB_REGS >= 16
160 #if TCG_TARGET_NB_REGS >= 32
183 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
186 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/tci/
H A Dtcg-target.h138 #define TCG_TARGET_NB_REGS 16 macro
151 #if TCG_TARGET_NB_REGS >= 16
160 #if TCG_TARGET_NB_REGS >= 32
183 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
186 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
H A Dtcg-target.inc.c283 #if TCG_TARGET_NB_REGS >= 16
312 #if TCG_TARGET_NB_REGS >= 16
332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
341 #if TCG_TARGET_NB_REGS >= 16
350 #if TCG_TARGET_NB_REGS >= 32
396 ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; in target_parse_constraint()
434 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); in tcg_out_r()
877 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
879 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
881 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
/dports/emulators/qemu42/qemu-4.2.1/tcg/tci/
H A Dtcg-target.h138 #define TCG_TARGET_NB_REGS 16 macro
151 #if TCG_TARGET_NB_REGS >= 16
160 #if TCG_TARGET_NB_REGS >= 32
183 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
186 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
H A Dtcg-target.inc.c283 #if TCG_TARGET_NB_REGS >= 16
312 #if TCG_TARGET_NB_REGS >= 16
332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
341 #if TCG_TARGET_NB_REGS >= 16
350 #if TCG_TARGET_NB_REGS >= 32
396 ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; in target_parse_constraint()
434 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); in tcg_out_r()
877 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
879 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
881 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/tci/
H A Dtcg-target.h136 #define TCG_TARGET_NB_REGS 16 macro
149 #if TCG_TARGET_NB_REGS >= 16
158 #if TCG_TARGET_NB_REGS >= 32
181 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
184 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
H A Dtcg-target.inc.c283 #if TCG_TARGET_NB_REGS >= 16
312 #if TCG_TARGET_NB_REGS >= 16
332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
341 #if TCG_TARGET_NB_REGS >= 16
350 #if TCG_TARGET_NB_REGS >= 32
395 ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; in target_parse_constraint()
433 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); in tcg_out_r()
875 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
877 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
879 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/tci/
H A Dtcg-target.h138 #define TCG_TARGET_NB_REGS 16 macro
151 #if TCG_TARGET_NB_REGS >= 16
160 #if TCG_TARGET_NB_REGS >= 32
183 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
186 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
H A Dtcg-target.inc.c283 #if TCG_TARGET_NB_REGS >= 16
312 #if TCG_TARGET_NB_REGS >= 16
332 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
341 #if TCG_TARGET_NB_REGS >= 16
350 #if TCG_TARGET_NB_REGS >= 32
396 ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1; in target_parse_constraint()
434 tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); in tcg_out_r()
877 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
879 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
881 tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; in tcg_target_init()
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/i386/
H A Dtcg-target.h31 # define TCG_TARGET_NB_REGS 16 macro
34 # define TCG_TARGET_NB_REGS 8 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/i386/
H A Dtcg-target.h31 # define TCG_TARGET_NB_REGS 16 macro
34 # define TCG_TARGET_NB_REGS 8 macro
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu5/qemu-5.2.0/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu42/qemu-4.2.1/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu60/qemu-6.0.0/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
36 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
37 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu/qemu-6.2.0/tcg/i386/
H A Dtcg-target.h33 # define TCG_TARGET_NB_REGS 32 macro
37 # define TCG_TARGET_NB_REGS 24 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
/dports/emulators/qemu/qemu-6.2.0/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
/dports/emulators/qemu60/qemu-6.0.0/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))

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