/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/mfd/ |
H A D | stm32-timers.h | 65 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ macro
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/dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/mfd/ |
H A D | stm32-timers.h | 65 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ macro
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/dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/mfd/ |
H A D | stm32-timers.h | 65 #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ macro
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/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_ll_tim.h | 497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32l1xx_hal_tim.h | 284 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 1023 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_ll_tim.h | 497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32l1xx_hal_tim.h | 284 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 1023 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_ll_tim.h | 497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32l1xx_hal_tim.h | 284 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 1023 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/ |
H A D | stm32l1xx_ll_tim.h | 497 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 1831 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 1832 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 2035 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 2063 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32l1xx_hal_tim.h | 284 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 1023 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/ |
H A D | stm32h7xx_ll_tim.c | 581 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init() 683 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_HALLSENSOR_Init() 855 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); in OC1Config() 1258 (TIM_CCER_CC1P | TIM_CCER_CC1NP), in IC1Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/ |
H A D | stm32g4xx_ll_tim.c | 563 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init() 665 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_HALLSENSOR_Init() 843 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); in OC1Config() 1255 (TIM_CCER_CC1P | TIM_CCER_CC1NP), in IC1Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/ |
H A D | stm32h7xx_ll_tim.h | 774 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 2581 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 2582 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 2785 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 2813 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32h7xx_hal_tim.h | 489 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 586 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compar… 1946 …ANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/src/ |
H A D | stm32f0xx_tim.c | 817 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); in TIM_OC1Init() 1734 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); in TIM_OC1NPolarityConfig() 3108 …tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CC… in TIM_EncoderInterfaceConfig() 3216 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TI1_Config()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/counter/ |
H A D | stm32-timer-cnt.c | 20 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/counter/ |
H A D | stm32-timer-cnt.c | 20 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/counter/ |
H A D | stm32-timer-cnt.c | 20 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
H A D | stm32f4xx_tim.c | 716 tmpccer &= (uint16_t)~TIM_CCER_CC1NP; in TIM_OC1Init() 1630 tmpccer &= (uint16_t)~TIM_CCER_CC1NP; in TIM_OC1NPolarityConfig() 3219 tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TI1_Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
H A D | stm32f4xx_tim.c | 716 tmpccer &= (uint16_t)~TIM_CCER_CC1NP; in TIM_OC1Init() 1630 tmpccer &= (uint16_t)~TIM_CCER_CC1NP; in TIM_OC1NPolarityConfig() 3219 tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TI1_Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/ |
H A D | stm32f37x_tim.c | 808 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); in TIM_OC1Init() 1641 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); in TIM_OC1NPolarityConfig() 3029 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TI1_Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/ |
H A D | stm32f37x_tim.c | 808 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); in TIM_OC1Init() 1641 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); in TIM_OC1NPolarityConfig() 3029 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TI1_Config()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/ |
H A D | stm32g4xx_ll_tim.h | 803 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is… 3439 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config() 3440 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config() 3643 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity() 3671 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
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H A D | stm32g4xx_hal_tim.h | 543 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T… 649 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compar… 2264 …ANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
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