Home
last modified time | relevance | path

Searched refs:TIM_CR2_MMS_1 (Results 1 – 25 of 34) sorted by relevance

12

/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal_tim.h606 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
607 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
610 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
611 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
H A Dstm32l1xx_ll_tim.h527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal_tim.h606 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
607 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
610 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
611 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
H A Dstm32l1xx_ll_tim.h527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal_tim.h606 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
607 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
610 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
611 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
H A Dstm32l1xx_ll_tim.h527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal_tim.h606 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
607 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
610 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
611 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
H A Dstm32l1xx_ll_tim.h527 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
528 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
531 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
532 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_hal_tim.h891 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update even…
892 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or …
895 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF sign…
896 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF sign…
H A Dstm32h7xx_ll_tim.h804 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
805 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
808 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
809 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_hal_tim.h1002 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update even…
1003 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or …
1006 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF sign…
1007 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF sign…
H A Dstm32g4xx_ll_tim.h839 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!<…
840 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
843 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!<…
844 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!<…
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4934 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h5012 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4934 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h3749 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h3749 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6807 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ macro
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6807 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ macro
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6807 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ macro
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6807 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A Dstm32f30x.h8419 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10444 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f4xx/
H A Dstm32f4xx.h10444 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/
H A Dstm32g431xx.h10001 #define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ macro

12