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Searched refs:TIM_SMCR_OCCS (Results 1 – 25 of 26) sorted by relevance

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/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected…
2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected…
2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected…
2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h763 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected…
2576 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); in LL_TIM_SetOCRefClearInputSource()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/
H A Dstm32g4xx_hal_tim.c5108 …CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM… in HAL_TIM_ConfigOCrefClear()
5137 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5168 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/
H A Dstm32f37x_tim.c1738 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); in TIM_SelectOCREFClear()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/
H A Dstm32f37x_tim.c1738 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); in TIM_SelectOCREFClear()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/src/
H A Dstm32f0xx_tim.c1884 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); in TIM_SelectOCREFClear()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/src/
H A Dstm32f30x_tim.c2022 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); in TIM_SelectOCREFClear()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_tim.h5347 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, in LL_TIM_SetOCRefClearInputSource()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4952 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selecti… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h5030 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selecti… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4952 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selecti… macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6824 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6824 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6824 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/
H A Dstm32l152xe.h6824 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A Dstm32f30x.h8446 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear sel… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/
H A Dstm32g431xx.h10058 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32gbk1cb.h10030 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32g441xx.h10289 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32g471xx.h10566 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32g473xx.h11340 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32g483xx.h11571 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro
H A Dstm32g474xx.h14702 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear sel… macro

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