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Searched refs:TIM_SR_UIF (Results 1 – 25 of 42) sorted by relevance

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/dports/devel/tinygo/tinygo-0.14.1/src/runtime/
H A Druntime_stm32f407.go196 if stm32.TIM3.SR.HasBits(stm32.TIM_SR_UIF) {
201 stm32.TIM3.SR.ClearBits(stm32.TIM_SR_UIF)
209 if stm32.TIM7.SR.HasBits(stm32.TIM_SR_UIF) {
211 stm32.TIM7.SR.ClearBits(stm32.TIM_SR_UIF)
H A Druntime_stm32f103xx.go198 if stm32.TIM3.SR.HasBits(stm32.TIM_SR_UIF) {
203 stm32.TIM3.SR.ClearBits(stm32.TIM_SR_UIF)
/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/mfd/
H A Dstm32-timers.h50 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/mfd/
H A Dstm32-timers.h50 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/mfd/
H A Dstm32-timers.h50 #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ macro
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32l1xx_hal_tim.h479 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32l1xx_hal_tim.h479 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32l1xx_hal_tim.h479 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_ll_tim.h312 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
2593 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
2604 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32l1xx_hal_tim.h479 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clocksource/
H A Dtimer-stm32.c42 #define TIM_SR_UIF BIT(0) macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clocksource/
H A Dtimer-stm32.c42 #define TIM_SR_UIF BIT(0) macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clocksource/
H A Dtimer-stm32.c42 #define TIM_SR_UIF BIT(0) macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/inc/
H A Dstm32h7xx_ll_tim.h505 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
3611 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
3622 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32h7xx_hal_tim.h702 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interru…
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/inc/
H A Dstm32g4xx_ll_tim.h523 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
5366 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
5377 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_UPDATE()
H A Dstm32g4xx_hal_tim.h784 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interru…
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4992 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Fla… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A Dstm32f0xx.h5070 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Fla… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A Dstm32f37x.h4992 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Fla… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h3805 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Fla… macro
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A Dstm32f10x.h3805 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Fla… macro

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