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Searched refs:TMR2 (Results 1 – 25 of 1824) sorted by relevance

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/dports/misc/gpsim/gpsim-0.31.0/regression/p16f91x/
H A Dpwm_914.asm127 .assert "tmr0 == 0x2f, 'TMR2 period'"
141 .assert "(portc & 0x20)==0, 'CCP1 is low TMR2 put, only change period'"
143 .assert "(portd & 0x04)==0, 'CCP2 is low TMR2 put, only change period'"
149 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
163 .assert "(portc & 0x20) == 0x00, 'CCP1 is low - TMR2 put between duty cycles'"
165 .assert "(portd & 0x04) == 0x04, 'CCP2 is high - TMR2 put between duty cycles'"
171 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
195 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
223 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
251 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
/dports/misc/gpsim/gpsim-0.31.0/regression/ccp/
H A Dpwm_26k22.asm119 .assert "ccpr1l != ccpr1h, '*** FAILED pwm_26k22 CCPR1H before TMR2 reset'"
163 .assert "tmr0 == 0x3f, '*** FAILED pwm_26k22 TMR2 period'"
176 .assert "(portc & 0x6) == 0x0, '*** FAILED pwm_26k22 TMR2 put, only change period'"
183 .assert "tmr0 == 0x22, '*** FAILED pwm_26k22 TMR2 put, only change period'"
189 .assert "tmr0 == 0x33, '*** FAILED pwm_26k22 TMR2 put, only change period'"
203 .assert "(portc & 0x6) == 0x2, '*** FAILED pwm_26k22 TMR2 put, between duty cycles'"
209 .assert "tmr0 == 0x23, '*** FAILED pwm_26k22 TMR2 put, between duty cycles'"
231 .assert "tmr0 == 0x80, '*** FAILED pwm_26k22 TMR2 > PR2 causes wrap'"
257 .assert "tmr0 == 0x10, '*** FAILED pwm_26k22 TMR2 period PR2 to 0x20'"
283 .assert "tmr0 == 0x88, '*** FAILED pwm_26k22 TMR2 period PR2 to 0x10 wraps'"
H A Dpwm_6520.asm113 .assert "ccpr1l != ccpr1h, '*** FAILED pwm_6520 CCPR1H before TMR2 reset'"
155 .assert "tmr0 == 0x3f, '*** FAILED pwm_6520 TMR2 period'"
168 .assert "(portc & 0x6) == 0x0, '*** FAILED pwm_6520 TMR2 put, only change period'"
175 .assert "tmr0 == 0x22, '*** FAILED pwm_6520 TMR2 put, only change period'"
181 .assert "tmr0 == 0x33, '*** FAILED pwm_6520 TMR2 put, only change period'"
195 .assert "(portc & 0x6) == 0x2, '*** FAILED pwm_6520 TMR2 put, between duty cycles'"
201 .assert "tmr0 == 0x23, '*** FAILED pwm_6520 TMR2 put, between duty cycles'"
223 .assert "tmr0 == 0x80, '*** FAILED pwm_6520 TMR2 > PR2 causes wrap'"
249 .assert "tmr0 == 0x10, '*** FAILED pwm_6520 TMR2 period PR2 to 0x20'"
275 .assert "tmr0 == 0x88, '*** FAILED pwm_6520 TMR2 period PR2 to 0x10 wraps'"
H A Dpwm_877a.asm125 .assert "tmr0 == 0x2f, '*** FAILED pwm_877a TMR2 period'"
139 .assert "(portc & 0x6) == 0x0, '*** FAILED pwm_877a TMR2 put, only change period'"
145 .assert "tmr0 == 0x23, '*** FAILED pwm_877a TMR2 put, only change period'"
159 .assert "(portc & 0x6) == 0x2, '*** FAILED pwm_877a TMR2 put, between duty cycles'"
165 .assert "tmr0 == 0x13, '*** FAILED pwm_877a TMR2 put, between duty cycles'"
189 .assert "tmr0 == 0x80, '*** FAILED pwm_877a TMR2 > PR2 causes wrap'"
217 .assert "tmr0 == 0x10, '*** FAILED pwm_877a TMR2 period PR2 to 0x20'"
245 .assert "tmr0 == 0x88, '*** FAILED pwm_877a TMR2 period PR2 to 0x10 wraps'"
/dports/misc/gpsim/gpsim-0.31.0/regression/p16f684/
H A Depwm.asm192 .assert "tmr0 == 0x2f, 'TMR2 period'"
206 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
212 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
226 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
232 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
256 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
279 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
302 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
/dports/misc/gpsim/gpsim-0.31.0/regression/p16f690/
H A Depwm.asm190 .assert "tmr0 == 0x2f, 'TMR2 period'"
204 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
210 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
224 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
230 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
254 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
277 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
300 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
/dports/misc/gpsim/gpsim-0.31.0/regression/epwm/
H A Dp16f887.asm187 .assert "tmr0 == 0x2f, 'TMR2 period'"
201 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
207 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
221 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
227 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
251 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
279 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
307 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
H A Dp18f4321.asm181 .assert "tmr0 == 0x2f, 'TMR2 period'"
195 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
201 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
215 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
221 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
244 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
270 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
296 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
H A Dp18f26k22.asm183 .assert "tmr0 == 0x2f, 'TMR2 period'"
197 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
203 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
217 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
223 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
246 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
272 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
298 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
H A Dp16f882.asm189 .assert "tmr0 == 0x2f, 'TMR2 period'"
203 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
209 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
223 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
229 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
253 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
281 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
309 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
H A Dp18f1220.asm175 .assert "tmr0 == 0x2f, 'TMR2 period'"
189 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
195 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
209 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
215 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
238 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
264 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
290 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
H A Dp18f2321.asm181 .assert "tmr0 == 0x2f, 'TMR2 period'"
195 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
201 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
215 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
221 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
244 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
270 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
296 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
/dports/misc/gpsim/gpsim-0.31.0/regression/p16f88x/
H A Depwm.asm187 .assert "tmr0 == 0x2f, 'TMR2 period'"
201 .assert "(portc & 0x6) == 0x0, 'TMR2 put, only change period'"
207 .assert "tmr0 == 0x23, 'TMR2 put, only change period'"
221 .assert "(portc & 0x6) == 0x2, 'TMR2 put, between duty cycles'"
227 .assert "tmr0 == 0x13, 'TMR2 put, between duty cycles'"
251 .assert "tmr0 == 0x80, 'TMR2 > PR2 causes wrap'"
279 .assert "tmr0 == 0x10, 'TMR2 period PR2 to 0x20'"
307 .assert "tmr0 == 0x88, 'TMR2 period PR2 to 0x10 wraps'"
/dports/editors/picpas/PicPas-7940bc3/devices16/
H A DPIC16C63.pas81 TMR2 : byte absolute $0011;
83 T2CON_TOUTPS3 : bit absolute TMR2.6;
84 T2CON_TOUTPS2 : bit absolute TMR2.5;
85 T2CON_TOUTPS1 : bit absolute TMR2.4;
86 T2CON_TOUTPS0 : bit absolute TMR2.3;
87 T2CON_TMR2ON : bit absolute TMR2.2;
88 T2CON_T2CKPS1 : bit absolute TMR2.1;
89 T2CON_T2CKPS0 : bit absolute TMR2.0;
/dports/misc/gpsim/gpsim-0.31.0/src/
H A D14bit-tmrs.h32 class TMR2; variable
266 void set_tmr2(TMR2 *_tmr2) { tmr2 = _tmr2; } in set_tmr2()
301 TMR2 *tmr2 = nullptr;
648 TMR2 *tmr2 = nullptr;
706 TMR2 *tmr2 = nullptr;
764 ~TMR2();
839 TMR2 *tmr2 = nullptr;
880 void set_tmr246(TMR2 *_t2, TMR2 *_t4, TMR2 *_t6) in set_tmr246()
895 TMR2 *t2 = nullptr;
896 TMR2 *t4 = nullptr;
[all …]
H A D16bit-tmrs.h139 void set_tmr246(TMR2 *t2, TMR2 *t4, TMR2 *t6);
147 TMR2 *t2 = nullptr, *t4 = nullptr, *t6 = nullptr;
H A D14bit-tmrs.cc2906 TMR2 *tmr2;
2910 TMR2::TMR2(Processor *pCpu, const char *pName, const char *pDesc) in TMR2() function in TMR2
2936 TMR2::~TMR2() in ~TMR2()
2947 void TMR2::callback_print() in callback_print()
2953 void TMR2::start() in start()
3106 void TMR2::update(int ut) in update()
3261 unsigned int TMR2::get() in get()
3273 unsigned int TMR2::get_value() in get_value()
3412 void TMR2::current_value() in current_value()
3455 void TMR2::callback() in callback()
[all …]
H A D16bit-tmrs.cc204 void CCPTMRS::set_tmr246(TMR2 *_t2, TMR2 *_t4, TMR2 *_t6) in set_tmr246()
/dports/misc/gpsim/gpsim-0.31.0/regression/interrupts_16bit/
H A Dpriority.asm301 bsf PIE1,TMR2IE ;Enable TMR2 overflow interrupts
323 bcf PIE1,TMR2IE ;Disable TMR2 overflow interrupts
324 clrf T2CON ; and switch off TMR2
395 .assert "'*** FAILED no TMR2 overflow detected'"
398 .assert "intflags == 4, '*** FAILED low priority TMR2 interrupt not masked'"
457 bsf PIE1,TMR2IE ;Enable TMR2 overflow interrupts
481 ;; high priority TMR2 interrupt with the "cause PORTB interrupt" flag set.
487 bsf temp5,7 ; TMR2 ISR triggers a PORTB event
496 btfss intflags,6 ; Wait for the TMR2 interrupt (must only see one)
502 bcf PIE1,TMR2IE ;Disable TMR2 overflow interrupts
[all …]
/dports/misc/gpsim/gpsim-0.31.0/regression/spi/
H A Dp16c62.asm227 .assert "(sspstat & 1) == 1, '*** FAILED p16c62 BSSP SPI Master TMR2, BF not set'"
230 .assert "(sspstat & 1) == 0, '*** FAILED p16c62 BSSP SPI Master TMR2, BF not cleared'"
232 .assert "W == 0x54, '*** FAILED p16c62 BSSP SPI Master TMR2 wrong data'"
H A Dp18f242.asm201 .assert "(sspstat & 1) == 1, 'FAILED MSSP SPI Master TMR2, BF not set'"
204 .assert "(sspstat & 1) == 0, 'FAILED MSSP SPI Master TMR2, BF not cleared'"
206 .assert "W == 0x54, 'FAILED MSSP SPI Master TMR2 wrong data'"
H A Dp16f88.asm234 .assert "(sspstat & 1) == 1, '*** FAILED p16f88 SSP SPI Master TMR2, BF not set'"
237 .assert "(sspstat & 1) == 0, '*** FAILED p16f88 SSP SPI Master TMR2, BF not cleared'"
239 .assert "W == 0x54, '*** FAILED p16f88 SSP SPI Master TMR2 wrong data'"
/dports/misc/gpsim/gpsim-0.31.0/regression/p12f675/
H A Dp12f683.asm127 ; Interrupt from TMR2
449 ;; -- TMR2 can be read and written
450 ;; -- TMR2 driven Fosc/4 with prescale of 8 and generates an interrupt
452 ; Load TMR2 with 0x80
453 BANKSEL TMR2
455 MOVWF TMR2
457 BCF PIR1,TMR2IF ;Clear any TMR2 pending interrupt
459 BSF PIE1,TMR2IE ;Enable TMR2 interrupts
466 BANKSEL TMR2
468 ; TMR2 not running yet, TMR2 should be unchanged
[all …]
/dports/misc/gpsim/gpsim-0.31.0/regression/p1xf18xx/
H A Dp16f1823_spi.asm244 .assert "(ssp1stat & 1) == 1, 'FAILED MSSP SPI Master TMR2, BF not set'"
248 .assert "(ssp1stat & 1) == 0, 'FAILED MSSP SPI Master TMR2, BF not cleared'"
250 .assert "W == 0x54, 'FAILED MSSP SPI Master TMR2 wrong data'"
/dports/misc/gpsim/gpsim-0.31.0/examples/projects/p16f628_test/
H A Df628.asm175 ;; TMR2 test
178 ;; with 0x40, 0x80, 0xc0, and 0x00 and wait for TMR2 to count up
199 bcf PIR1,TMR2IF ;tmr2if is set when TMR2 finishes count

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