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Searched refs:TRAP_VECTOR_START (Results 1 – 16 of 16) sorted by relevance

/dports/devel/avr-gdb/gdb-7.3.1/sim/cr16/
H A Dcr16_sim.h457 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c5069 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_C_C()
/dports/devel/gdb761/gdb-7.6.1/sim/cr16/
H A Dcr16_sim.h457 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c5071 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_C_C()
/dports/devel/avr-gdb/gdb-7.3.1/sim/d10v/
H A Dd10v_sim.h478 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c3197 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_5F00()
H A DChangeLog655 SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
/dports/devel/gdb761/gdb-7.6.1/sim/d10v/
H A Dd10v_sim.h478 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c3197 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_5F00()
H A DChangeLog690 SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/
H A Dd10v_sim.h478 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c3197 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_5F00()
H A DChangeLog575 SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/d10v/
H A Dd10v_sim.h478 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ macro
H A Dsimops.c3197 uint16 vec = OP[0] + TRAP_VECTOR_START; in OP_5F00()
H A DChangeLog575 SDBT_VECTOR_START, TRAP_VECTOR_START): Define.